View MT90868_2037946.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 zarlink semiconductor inc. features ? 32,768-channel x 8,192-channel blocking switching between backplane and local streams ? 8,192-channel x 8,192-channel non-blocking switching for local input and output streams ? 1,024-channel x 1,024-channel switch between two selected backplane input and output streams ? rate conversion between backplane and local streams ? accepts st-bus streams with data rate of 16.384mb/s or 32.768mb/s for backplane port ? accepts st-bus streams with data rate of 8.192mb/s for local port ? per-stream channel and bit delay for the local input streams ? per-stream channel and bit advancement for the local output streams ? per-stream bit delay for the backplane input streams ? per-stream bit advancement for the backplane output streams ? per-channel constant throughput delay ? per-channel high impedance output control for local streams ? per-channel high impedance or driven-high output control for backplane streams ? per-channel message mode for backplane and local output streams ? pseudo-random binary sequence (prbs) pattern generation and testing for local and backplane ports ? non-multiplexed micr oprocessor interface ? connection memory blo ck programming for fast device initialization ? tristate-control outputs for external drivers on local port december 2002 ordering information MT90868ag 466 ball-pbga -40 to +85 c MT90868 high bandwidth digital switch data sheet figure 1 - functional block diagram fp4o c4o c8o c16o fp8o fp16o ds cs r/w a15-a0 dta d15-d0 test port microprocessor interface and internal registers backplane data memories v ss (gnd) v dd_core tdi tdo tck trst tms lsto0-63 (32,768 channels) (8,192 reset connection local timing output mux output mux apll lsti0-63 local data (8,192 channels) backplane (32,768 locations) local loopback data memory c8i at1 dt1 tm1 tm2 sg1 v dd_io lcsto0-3 ic0-ic5 ode unit (1,024 channels) connection memory input channel delay buffer memory output channel advancement buffer locations) mux mux mux memories local interface p/s converter local interface s/p converter bsti0-63 backplane timing unit fp8i interface backplane converter s/p interface backplane converter p/s bsto0-63 bit bit multiplexer de-multiplexer mux mux bime
MT90868 data sheet 2 zarlink semiconductor inc. ? conforms to the mandatory requirements of the ieee-1149.1 (jtag) standard ? 1.8v core supply voltage ? 3.3v i/o supply voltage wi th 5v tolerant i/o?s applications ? mediation switches ? high capacity tdm switching plat forms utilizing ds-3/oc-3 rates ? central office switches ? access equipment description the MT90868 digital switch provides switching capacities of 32,768 x 8,192 channels between backplane and local streams, 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams. the local port has sixty-fo ur input and sixty-four output stre ams which operate at 8.192mb/s. the backplane port has sixty-four input and sixty-four output streams wh ich operate at 16.384mb/s or 32.768mb/s. the MT90868 has features that are programmable on pe r-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughpu t delay, high impedance output control for both local and backplane streams and the driven-high backplane output control.
data sheet MT90868 3 zarlink semiconductor inc. figure 2 - 35mm x 35mm pbga (jedec mo-151) pinout vss vss vss vss vss vss vss vss vss vss vss vss vss vss 35791113151719212325 1 - a1 corner is identified by metallized markings. a 1 2468101214161820222426 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vdd_ io vdd_ io vdd_ io vdd_ io vdd_ io vdd_ vdd_ io vdd_ io vdd_ io vdd_ io vdd_ io vdd_ io vss vss vss vss vss vss vss vdd_ io vdd_ core vss vss vss vss vdd_ io vdd_ core vss vdd_ core vdd_ core vdd_ io vdd_ core vdd_ io vdd_ core vdd_ core vdd_ io vdd_ core vss vdd_ io vdd_ io vdd_ io vdd_ core vdd_ core vdd_ core core vdd io vdd_ io vdd_ core vdd_ core clk vdd_ io vdd_ core vdd_ core vdd_ core vss vdd_ core bsto _10 bsto _11 bsto _12 bsto _13 bsto _14 bsto _15 bsti _16 bsti _17 bsti _18 bsti _19 bsti _21 bsti _23 bsti _22 bsti _20 bsto _16 bsto _17 bsto _8 bsto _ 9 bsto _18 bsto _19 bsto _20 bsto _21 bsto _22 bsto _23 bsti _24 bsti _25 bsti _26 bsti _27 bsti _28 bsti _29 bsti _30 bsti _31 bsto bsto _24 bsto _25 bsto _26 bsto _27 bsto _28 bsto _29 bsto _30 bsto _31 bsti bsti bsti bsti bsti bsti bsti bsti _32 _33 _34 _35 _36 _37 _38 _39 bsto bsto bsto bsto bsto bsto bsto bsto _32 _33 _34 _35 _36 _37 _38 _39 bsti bsti bsti bsti bsti bsti bsti bsti _40 _41 _42 _43 _44 _45 _46 _47 bsto bsto bsto bsto bsto bsto bsto _40 _41 _42 _44 _45 _46 _47 bsto _43 bsti _48 bsti bsti bsti bsti bsti _49 _50 bsti _51 _52 _53 _54 bsti _55 bsto bsto bsto bsto bsto bsto bsto bsto _48 _49 _50 _51 _52 _53 _54 _55 bsti bsti bsti bsti bsti bsti bsti bsti _56 _57 _58 _59 _60 _61 _62 _63 bsto bsto bsto bsto bsto bsto bsto bsto _56 _57 _58 _59 _60 _61 _62 _63 fp8i a4 bsti _0 bsti _1 bsti _2 bsti _3 bsti _4 bsti _5 bsti _6 bsti _7 bsti _8 bsti _9 bsti _10 bsti _11 bsti _12 bsti _13 bsti _15 bsti _14 bsto _0 bsto _1 bsto _2 bsto _3 bsto _4 bsto _5 bsto _6 bsto _7 r/w a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 dta tms ode lsti _0 lsti _1 lsti _2 lsti _3 lsti _4 lsti _5 lsti _6 lsti _7 lsto lsto _1 lsto _2 lsto _3 lsto _4 lsto _5 lsto _6 lsto _7 lsti _8 lsti _9 lsti _10 lsti _11 lsti _12 lsti _13 lsti _14 lsti _15 lsto _8 lsto _9 lsto _10 lsto _11 lsto _12 lsto _13 lsto _14 lsto _15 lsti _16 lsti _17 lsti _18 lsti _20 lsti _21 lsti _23 lsto _16 lsto _17 lsti _22 lsti _19 lsto _18 lsto _19 lsto _20 lsto _21 lsto _22 lsto _23 lsti _24 lsti _25 lsti _26 lsti _27 lsti _28 lsti _29 lsti _30 lsti _31 lsto _24 lsto _25 lsto _26 lsto _27 lsto _28 lsto _29 lsto _30 lsto _31 lsti _32 lsti _33 lsti _34 lsti _35 lsti _36 lsti _37 lsti _38 lsti _39 lsto _32 lsto _33 lsto _34 lsto _35 lsto _36 lsto _37 lsto _38 lsto _39 lsti _40 lsti _41 lsti _42 lsti _43 lsti _44 lsti _45 lsti _46 lsti _47 lsto _40 lsto _41 lsto _42 lsto _43 lsto _44 lsto _45 lsto _46 lsto _47 lsti _48 lsti _49 lsti _50 lsti _51 lsti _52 lsti _53 lsti _54 lsti _55 lsto _48 lsto _49 lsto _50 lsto _51 lsto _52 lsto _53 lsto _54 lsto _55 lsti _56 lsti _57 lsti _58 lsti _59 lsti _60 lsti _61 lsti _62 lsti _63 lsto _56 lsto _57 lsto _58 lsto _59 lsto _60 lsto _61 lsto _62 lsto _63 ic3 ic4 ic5 tck tdi trst reset tdo ic0 ic1 ic2 vdd_ core vss vdd_ vss vdd_ core a9 a6 a2 a3 a11 dt1 c8i a0 sg1 tm2 tm1 at1 byps top view vdd_ core lcs to_0 lcs to_1 lcs to_2 lcs to_3 a7 a5 a10 a8 bime io a5 a1 ds c4o c8o c16o cs fp fp fp 4o 8o 16o _0 vss vss vss vss 35791113151719212325 2 4 6 8 101214161820222426 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
MT90868 data sheet 4 zarlink semiconductor inc. ball signal assignment ball number signal name a1 bsto8 a2 bsto9 a3 bsti13 a4 bsti11 a5 bsti9 a6 bsto6 a7 bsto3 a8 bsto1 a9 bsti6 a10 bsti3 a11 tdi a12 tck a13 tdo a14 lsti62 a15 lsti61 a16 lsti59 a17 lsti57 a18 lsti54 a19 lsti53 a20 lsti50 a21 lsto47 a22 lsto46 a23 lsti47 a24 lsti46 a25 lsti44 a26 lsti42 b1 bsto10 b2 bsto11 b3 bsti14 b4 bsti10 b5 bsti8 b6 bsto5 b7 bsto2 b8 bsto0 b9 bsti5 b10 bsti1 b11 trst b12 tms b13 reset b14 lsti63 b15 lsti60 b16 lsti58 b17 lsti56 b18 lsti55 b19 lsti52 b20 lsti49 b21 lsto45 b22 lsto44 b23 lsti45 b24 lsti43 b25 lsti41 ball number signal name b26 lsti40 c1 bsto13 c2 bsto12 c3 bsti15 c4 bsti12 c5 bsto7 c6 bsto4 c7 ic3 c8 bsti7 c9 bsti4 c10 bsti2 c11 bsti0 c12 lsto63 c13 lsto60 c14 lsto59 c15 lsto57 c16 lsto55 c17 lsto53 c18 lsto51 c19 lsti51 c20 lsti48 c21 lsto43 c22 lsto42 c23 lsto41 c24 lsto40 c25 lsto39 ball number signal name
data sheet MT90868 5 zarlink semiconductor inc. c26 lsto38 d1 bsto15 d2 bsto14 d3 bsti16 d4 gnd d5 vdd_io d6 gnd d7 ic4 d8 ic5 d9 ic1 d10 ic2 d11 ic0 d12 lsto62 d13 lsto61 d14 lsto58 d15 lsto56 d16 lsto54 d17 lsto52 d18 lsto50 d19 lsto49 d20 lsto48 d21 gnd d22 vdd_io d23 gnd d24 lsto37 d25 lsto36 ball number signal name d26 lsto35 e1 bsti19 e2 bsti18 e3 bsti17 e4 vdd_io e7 vdd_core e8 gnd e9 vdd_io e10 gnd e11 vdd_io e12 vdd_core e13 gnd e14 gnd e15 vdd_core e16 vdd_io e17 gnd e18 vdd_io e19 gnd e20 vdd_core e23 vdd_io e24 lsto34 e25 lsto33 e26 lsto32 f1 bsti22 f2 bsti21 f3 bsti20 ball number signal name f4 gnd f23 gnd f24 lsti39 f25 lsti38 f26 lsti37 g1 bsto17 g2 bsto16 g3 bsti23 g4 vdd_core g23 vdd_core g24 lsti36 g25 lsti35 g26 lsti34 h1 bsto21 h2 bsto20 h3 bsto19 h4 bsto18 h5 gnd h22 gnd h23 vdd_io h24 lsto31 h25 lsti33 h26 lsti32 j1 bsto22 j2 bsto23 j3 bsti25 ball number signal name
MT90868 data sheet 6 zarlink semiconductor inc. j4 bsti24 j5 vdd_io j22 vdd_core j23 lsto30 j24 lsto29 j25 lsti31 j26 lsti28 k1 bsto25 k2 bsto24 k3 bsti27 k4 bsti26 k5 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd k16 gnd k17 gnd k22 lsto28 k23 lsto27 k24 lsto26 k25 lsti30 k26 lsti27 l1 bsto27 ball number signal name l2 bsto26 l3 bsti28 l4 bsti29 l5 vdd_io l10 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l17 gnd l22 vdd_io l23 lsto24 l24 lsto25 l25 lsti29 l26 lsti26 m1 bsto29 m2 bsto28 m3 bsti30 m4 bsti31 m5 vdd_core m10 gnd m11 gnd m12 gnd m13 gnd ball number signal name m14 gnd m15 gnd m16 gnd m17 gnd m22 vdd_core m23 lsto23 m24 lsto22 m25 lsti25 m26 lsti24 n1 bsto30 n2 bsto31 n3 bsti33 n4 bsti32 n5 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n22 vdd_io n23 lsto21 n24 lsto20 n25 lsti23 ball number signal name
data sheet MT90868 7 zarlink semiconductor inc. n26 lsti20 p1 bsto33 p2 bsto32 p3 bsti34 p4 bsti35 p5 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p22 gnd p23 lsto18 p24 lsto19 p25 lsti22 p26 lsti19 r1 bsto35 r2 bsto34 r3 bsti37 r4 bsti36 r5 vdd_core r10 gnd r11 gnd ball number signal name r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd r22 vdd_core r23 lsto17 r24 lsto16 r25 lsti21 r26 lsti18 t1 bsto37 t2 bsto36 t3 bsti39 t4 bsti38 t5 vdd_io t10 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd t22 vdd_io t23 lsto15 ball number signal name t24 lsto14 t25 lsti17 t26 lsti16 u1 bsto38 u2 bsto39 u3 bsti40 u4 bsti41 u5 gnd u10 gnd u11 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd u22 gnd u23 lsto12 u24 lsto13 u25 lsti15 u26 lsti12 v1 bsto41 v2 bsto40 v3 bsti42 v4 bsti45 v5 vdd_io ball number signal name
MT90868 data sheet 8 zarlink semiconductor inc. v22 vdd_core v23 lsto8 v24 lsto11 v25 lsti14 v26 lsti11 w1 bsto43 w2 bsto42 w3 bsti43 w4 bsti47 w5 gnd w22 gnd w23 vdd_io w24 lsto10 w25 lsti13 w26 lsti10 y1 bsto45 y2 bsto44 y3 bsti44 y4 vdd_core y23 vdd_core y24 lsto9 y25 lsti9 y26 lsti8 aa1 bsto46 aa2 bsto47 aa3 bsti46 ball number signal name aa4 gnd aa23 gnd aa24 lsto7 aa25 lsto6 aa26 lsto5 ab1 bsti48 ab2 bsti49 ab3 bsti50 ab4 vdd_io ab8 gnd ab9 vdd_io ab10 gnd ab11 vdd_core ab12 gnd ab13 vdd_core ab14 gnd ab15 vdd_core ab16 vdd_io ab17 gnd ab18 vdd_io ab19 gnd ab23 vdd_io ab24 lsto4 ab25 lsto3 ab26 lsto2 ac1 bsti51 ball number signal name ac2 bsti52 ac3 bsti53 ac4 vdd_core ac5 vdd_io ac6 gnd ac7 vdd_core ac8 fp8i ac9 a4 ac10 a7 ac11 a5 ac12 vdd_core ac13 a10 ac14 a9 ac15 a14 ac16 d3 ac17 d7 ac18 d11 ac19 d15 ac20 vdd_core ac21 gnd ac22 gnd ac23 gnd ac24 lsto1 ac25 lsti7 ac26 lsti6 ad1 bsti54 ball number signal name
data sheet MT90868 9 zarlink semiconductor inc. ad2 bsti55 ad3 bsti57 ad4 bsti56 ad5 bsti58 ad6 bsti62 ad7 ode ad8 bime ad9 a8 ad10 a6 ad11 a1 ad12 a2 ad13 a3 ad14 a11 ad15 a15 ad16 d2 ad17 d6 ad18 d10 ad19 d14 ad20 lcsto0 ad21 lcsto1 ad22 lcsto2 ad23 lcsto3 ad24 lsto0 ad25 lsti5 ad26 lsti4 ae1 bsto48 ball number signal name ae2 bsto50 ae3 bsto53 ae4 bsto54 ae5 bsti59 ae6 bsti63 ae7 bsto56 ae8 bsto59 ae9 bsto63 ae10 bsto62 ae11 dt1 ae12 c8i ae13 clkbyps ae14 a0 ae15 a13 ae16 d1 ae17 d5 ae18 d9 ae19 d13 ae20 dta ae21 ds ae22 c4o ae23 c8o ae24 c16o ae25 lsti3 ae26 lsti2 af1 bsto49 ball number signal name af2 bsto51 af3 bsto52 af4 bsto55 af5 bsti60 af6 bsti61 af7 bsto57 af8 bsto58 af9 bsto60 af10 bsto61 af11 sg1 af12 tm2 af13 tm1 af14 at1 af15 a12 af16 d0 af17 d4 af18 d8 af19 d12 af20 r/w af21 cs af22 fp4o af23 fp8o af24 fp16o af25 lsti0 af26 lsti1 ball number signal name
MT90868 data sheet 10 zarlink semiconductor inc. pin description pbga ball number name description e12, e15, e20, e7, g23, g4, j22, m22, m5, r22, r5, v22, y23, y4, ab11, ab13, ab15, ac20, ac4, ac7. v dd_core power supply for core logic circuits: +1.8v d22, d5, e11, e16, e18, e23, e4, e9, h23, j5, l22, l5, n22, t22, t5, v5, w23, ab16, ab18, ab23, ab4, ab9, ac5. v dd_io power supply for pads: +3.3v. the v dd_io supply has to be either established before the power up of the v dd_core supply or the v dd_core should not "lead" the v dd_io by more than 0.3v. m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, n5, p10, p11, p12, p13, p14, p15, p16, p17, p22, p5, r10, r11, r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17, u22, u5, w22, w5. v ss (gnd) ground c11, b10, c10, a10, c9, b9, a9, c8, b5, a5, b4, a4, c4, a3, b3, c3, d3, e3, e2, e1, f3, f2, f1, g3, j4, j3, k4, k3, l3, l4, m3, m4, n4, n3, p3, p4, r4, r3, t4, t3, u3, u4, v3, w3, y3, v4, aa3, w4, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad4, ad3, ad5, ae5, af5, af6, ad6, ae6. bsti0 - 63 backplane serial input streams 0 to 63 (5v tolerant inputs): in 16mb/s mode, these pins accept serial tdm data streams at 16.384 mb/s with 256 channels per stream. in 32mb/s mode, these pins accept serial tdm data streams at 32.768 mb/s with 512 channels per stream. b8, a8, b7, a7, c6, b6, a6, c5, a1, a2, b1, b2, c2, c1, d2, d1, g2, g1, h4, h3, h2, h1, j1, j2, k2, k1, l2, l1, m2, m1, n1, n2, p2, p1, r2, r1, t2, t1, u1, u2, v2, v1, w2, w1, y2, y1, aa1, aa2, ae1, af1, ae2, af2, af3, ae3, ae4, af4, ae7, af7, af8, ae8, af9, af10, ae10, ae9. bsto0 - 63 backplane serial output streams 0 to 63 (5v tolerant three-state outputs): in 16mb/s mode, these pins have data rate of 16.384 mb/s with 256 channels per stream. in 32mb/s mode, these pins have data rate of 32.768 mb/s with 512 channels per stream. ac8 fp8i frame pulse input (5v tolerant input): this pin accepts the backplane frame pulse which is low for 122ns (one 8.192mhz period) at the frame boundary. the frame pulse frequency is 8khz. ae12 c8i master clock input (5v tolerant input): this pin accepts an 8.192mhz clock. the clock falling edge is aligned with the backplane frame boundary. this input must be provided for any function to operate. ae13 clkbyps apll bypass clock (5v tolerant input): this pin accepts a 131.072mhz clock for device testing purpose. in normal operation, this input must be low.
data sheet MT90868 11 zarlink semiconductor inc. af13 tm1 apll test pin 1 (3.3v tolerant input): used for apll testing only. in normal operation, this input must be low. af12 tm2 apll test pin 2 (3.3v tolerant input): used for apll testing only. in normal operation, this input must be low. af11 sg1 apll test control (3 .3v tolerant input): used for apll testing only. in normal operation, this input must be low. af14 at1 analog test access (3.3v tolerant i/o): used for apll testing only. this pin is pulled low by an internal pull-down resistor. no connection for normal operation. ae11 dt1 digital test acce ss (3.3v output): used for apll testing only. no connect for normal operation. af21 cs chip select (5v tolerant input): active low input used by the microprocessor to enable the microprocessor port access. ae21 ds data strobe (5v tolerant input): this active low input works in conjunction with cs to enable the microprocessor port read and write operations. af20 r/w read/write (5v tolerant input): this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. ae14, ad11, ad12, ad13, ac9, ac11, ad10, ac10, ad9, ac14, ac13, ad14, af15 , ae15, ac15, ad15. a0 - a15 address 0 - 15 (5v tolerant inputs): these pins form the 16-bit address bus of the microprocessor port. af16, ae16, ad16, ac16, af17, ae17, ad17, ac17, af18, ae18, ad18, ac18, af19 , ae19, ad19, ac19. d0 - d15 data bus 0 - 15 (5v tolerant i/os): these pins form the 16-bit data bus of the microprocessor port. ae20 dta data transfer acknowledgment (5v tolerant output): this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold at high level. b12 tms test mode select (5v tolerant input with in ternal pull- up): jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull- up resistor when it is not driven. a12 tck test clock (5v tolerant input): provides the clock to the jtag test logic. a11 tdi test serial data in (5v input with internal pull-up): jtag serial test inst ructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up resistor when it is not driven. pin description (continued) pbga ball number name description
MT90868 data sheet 12 zarlink semiconductor inc. a13 tdo test serial data out (5v to lerant three-state output): jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. b11 trst test reset (5v tolerant in put with internal pull-up): asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. b13 reset device reset (5v tolerant input with internal pull-up): this input (active low) puts the device in its reset state that disables the lsto0 - 63 driver and drives the bsto0 - 63, lcsto-3 outputs to high. it also clears the device registers and internal counters. to ensure proper reset action, the reset pin must be held low for longer than 500ns. a delay of 100 s must also be applied before the first microprocessor access is performed after the reset pin is set high, this delay is required for the initialization of the apll. d11 ic0 in normal operation, this input must be connected to ground. d9 ic1 in normal operation, this input must be connected to ground. d10 ic2 in normal operation, this input must be connected to ground. c7 ic3 in normal operation, this input must be connected to ground. d7 ic4 in normal operation, this input must be connected to ground. d8 ic5 in normal operation, this input must be connected to ground. af25, af26, ae26, ae25, ad26, ad25, ac26, ac25, y26, y25, w26, v26, u26, w25, v25, u25,t26,t25, r26, p26, n26, r25, p25, n25, m26, m25, l26, k26, j26, l25, k25, j25, h26, h25, g26, g25, g24, f26, f25, f24, b26, b25, a26, b24, a25, b23, a24, a23, c20, b20, a20, c19, b19, a19, a18, b18, b17, a17, b16, a16, b15, a15, a14, b14. lsti0 - 63 local serial input streams 0 to 63 (5v tolerant inputs): these inputs accept data rates of 8.192 mb/s with 128 channels per stream. pin description (continued) pbga ball number name description
data sheet MT90868 13 zarlink semiconductor inc. ad24, ac24, ab26, ab25, ab24, aa26, aa25, aa24, v23, y24, w24, v24, u23, u24, t24, t23, r24, r23, p23, p24, n24, n23, m24, m23, l23, l24, k24, k23, k22, j24, j23, h24, e26, e25, e24, d26, d25, d24, c26, c25, c24, c23, c22, c21, b22, b21, a22, a21, d20, d19, d18, c18, d17, c17, d16, c16, d15, c15, d14, c14, c13, d13, d12, c12 lsto0 - 63 local serial output streams 0 to 63 (5v tolerant three-state outputs): these outputs have data rates of 8.192 mb/s with 128 channels per stream. ae24 c16o local c16o clock (3.3v three-state output): a 16.384mhz clock output. the clock falling edge is aligned with the local frame boundary. ae23 c8o local c8o clock (3.3v thre e-state output): a 8.192mhz clock output. the clock falling edge is aligned with the local frame boundary. ae22 c4o local c4o clock (3.3v thre e-state output): a 4.096mhz clock output. the clock falling edge is aligned with the local frame boundary. af24 fp16o local st-bus frame pulse output (3.3v three-state output): local port st-bus frame pulse output which is low for 61ns at the frame boundary. its frequency is 8khz. af23 fp8o local ct-bus frame pulse output (3.3v three-state output): local port st-bus frame pulse output which is low for 122ns at the frame boundary. its frequency is 8khz. af22 fp4o local st-bus frame pulse output (3.3v three-state output): local port st-bus frame pulse output which is low for 244ns at the frame boundary. its frequency is 8khz. ad20- ad23 lcsto0 - 3 local tristate control streams 0 to 3 (3.3v three-state outputs): these pins are used for per-channel external tristate control of the local ou tput streams. the bit rate is 16.384mhz. when reset pin or ode pin is low, the lcsto0 - 3 are driven high. ad7 ode output drive enable (5v tolerant input): this is the asynchronously output enable control for the bsto0 - 63 and lsto0 - 63 serial outputs. when it is high, the bsto0 - 63, lsto0 - 63 and lcsto0-3 are enabled. when it is low, the bsto0 - 63 are tristated or driven high, the lsto0 - 63 are tristated and the lcsto0 - 3 are driven high. pin description (continued) pbga ball number name description
MT90868 data sheet 14 zarlink semiconductor inc. ad8 bime bit interleaving mode enable (5v tolerant input with internal pull down): when bime and the bms bit in the control register are both high, the bit interleaving mode is enabled. see figure 26 for the bit interleaving mode timing diagram. when it is low, the bit interleaving mode is disabled and the bms bit in the control register selects the 16mb/s or 32mb/s mode for the backplane streams. pin description (continued) pbga ball number name description
data sheet MT90868 15 zarlink semiconductor inc. 1.0 device overview the MT90868 can switch up to 32,768 8,192 channels while providing a rate conversion capability. it is designed to switch 64 kb/s pcm or n x 64 kb/s data between the backplane and local switching applications. the device maintains frame integrity in data applications and mini mum throughput delay for voice application on a per channel basis. the backplane interface can operate at 16.384mb/s or 32.768mb/s on st-bus and is arranged in 125 s wide frames that contain 256 or 512 channels respectively. a bu ilt-in rate conversion circuit allows users to interface between backplane and local interfaces which operates at 8.192mb/s. by using zarlink?s message mode capability, the microprocessor can access input and output time slots on a per channel basis. this feature is useful for transferring contro l and status information for ex ternal circuits or other st- bus devices. 1.1 functional description a functional block diagram of the MT90868 is shown in figu re 1. it is designed to inte rface st-bus serial streams from a backplane source and st-bus serial streams from a local source. 1.2 frame alignment timing in the st-bus mode, the c8i pin accepts a 8.192mhz clock for the frame pulse alignment. the fp8i is a 8khz frame pulse signal which goes low at the frame boundary for 122ns. the frame boundary is defined by the falling edge of the c8 i clock during the low cycle of the frame pulse. figure 3 shows the backplane port timing diagram with the data rate of 16mb/s and 32mb/s. the bfp8c bit in the block programming mode register ( bpr) allows the device to accept different frame pulse formats. if the bfp8c bit in the block programming register is low, the device accepts a negative frame pulse. if the bfp8c bit is high, the device accepts a positive frame pulse as described in figure 3. the device accepts the backplane frame pulse input and generates the local frame pulse outputs. when the 16mb/s or 32 mb/s mode is selected for the backplane port, the delay between the backplane and local frame pulse signals is two 16mb/s or 32mb/s backplane channels plus 10 cycles of c8i resp ectively. figures 4 and 5 show the backplane and local frame pulse alignment for the 16mb/s and the 32mb/s timing mode respectively. 1.3 local interface output timing the local frame pulses, fp4o , fp8o and fp16o are 8khz output signals that have a pulse width of 244ns, 122ns and 61ns respectively at the frame boundary. the frame boundary is defi ned by the falling edge of the c8o output clock during the low cycle of the frame pulse fp8o . at the frame boundary, the falling edges of the c4o and c16o output clocks are aligned with the falling edge of the c8o output clock. in addition, the c8o clock can be inverted by programming the c8c bit to high in the bpr register. when the lfp4c, lfp8c and lfp16c bits are programmed to high in the bpr register, the device will provide positive frame pulse for the fp4o , fp8o and fp16o outputs. the local port timing diagram is shown in figure 6.
MT90868 data sheet 16 zarlink semiconductor inc. . figure 3 - backplane port timing diagram for 16mb/s and 32mb/s modes figure 4 - backplane and local frame pulse alignment, backplane data rate is 16mb/s figure 5 - backplane and local frame pulse alignment, backplane date rate is 32mb/s fp8i (8.192mhz) 72 3 4 5 610 0 bsti/bsto0-63 (16mb/s) 1 2 3 4 5 610 7 channel 255 channel 0 c8i 72 3 4 5 610 bsti/bsto0-63 (32mb/s) channel 0 72 3 4 5 610 channel 1 2 310 72 3 4 5 610 channel 511 2 3 4 5 610 channel 510 76 (8khz) bfp8c = 0 bfp8c = 1 fp8i 7 2 3 4 5 6 10 channel 0 72 3 4 5 610 channel 1 2 310 7 2 3 4 5 6 10 channel 4 2 3 4 5 610 channel 3 76 7 channel 2 2 3 4 51 bsti/bsto0-63 (16mb/s) fp8i c8i c8o fp8o 17 06 channel 126 3 4 52 lsti/lsto0-63 (8mb/s) 17 06 channel 127 3 4 52 17 0 ch0 2 ch255 two (16mb/s) channels + ten c8i cycles channel 125 ch 0 ch 1 1 bsti/bsto0-63 (32mb/s) ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 ch 8 fp8i c8i fp8o c8o 5 3 4 2 channel 126 7 0 16 lsti/lsto0-63 (8mb/s) 5 3 4 2 channel 127 7 0 16 5 3 4 channel 0 6 ch 511 two (32mb/s) channels + ten c8i cycles
data sheet MT90868 17 zarlink semiconductor inc. figure 6 - local port timing diagram fp4o (4.096mhz) c4o (8khz) (8.192mhz) c8o (16.384mhz) c16o 72 3 4 5 610 lsti/lsto0-63 (8mb/s) channel 0 72 3 4 5 610 channel 1 2 310 72 3 4 5 610 channel 127 2 3 4 5 610 channel 126 76 fp8o fp16o lfp16c = 0 fp4o lfp4c = 1 lfp4c = 0 fp8o lfp8c = 1 lfp8c = 0 fp16o lfp16c = 1 (8.192mhz) c8o c8c=0 c8c=1
MT90868 data sheet 18 zarlink semiconductor inc. 2.0 switching configuration the MT90868 has two operation modes at different data rates for the backplane interface and one operation mode for the local interface. the two operation modes for the ba ckplane interface can be selected via the backplane mode selection bit (bms) in th e control register (cr). 2.1 backplane interface the backplane interface can be programmed to accept data streams of 16mb/s or 32mb/s. when bms bit of the cr register is low, the 16mb/s mode is enabled, bsti0-63 and bsto0-63 have a data rate of 16.384mb/s. when bms = 1, the 32mb/s mode is enabled, bsti0-63 and bsto0-63 have a data rate of 32.768mb/s. table 1 describes the data rates and mode selections for the backplane interface. 2.2 local interface the local interface has one mode of operation whic h can only operate at the data rate of 8.192mb/s. 2.3 output bit advancement selection the device allows users to advance individual backplane or local output streams with respect to the frame boundary. this feature is useful in compensating variable output delays caused by various output loading conditions. each output stream can have its own advancement value pr ogrammed by the output ad vancement registers. the backplane output advancement registers (boar0 to boar7) are used to program the backplane output advancement. the local output advancement registers (loa r0 to loar7) are used to program the local output advancement. see tables 17 and table 19 for the descriptions of the loar and boar registers. possible adjustment for local is -1/8, -1/4 or -3/8 bit and the resolution is 1/8 bit (or 1/8 of c8o cycle). for backplane, the possible adjustment is -1/4, -1/2 or -3/4 bit when the output data rate is 16.384mb/s. when the backplane data rate is 32.768mb/s, the possible adjustment is -1/2, -1 or -1 1/2 bi t. for both data rates, the resolution is 1/8 of c8 i cycle. the advancement is inde pendent of the output data ra te. figures 7, 8 and 9 descr ibe the details of the output advancement programming for the local and the backplane interfaces respectively. 2.4 input bit delay selection the MT90868 input bit delay features allow users to have mo re flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on pcm highways which are connected to the switch matrix cards. each input data stream can have its own input bit delay value programmed by the input delay registers. the local input delay registers (lidr0 - lidr21) are used to pr ogram the local input delay. the backplane input delay registers (bidr0 - bidr21) are used to program the backplane input delay. see tables 8, 12 and tables 14, 15 for the descriptions of the lidr and bidr registers. bms bit of the control register modes backplane interface 0 16.384mb/s bsti0 - 63 and bsto0 - 63 1 32.768mb/s bsti0 - 63 and bsto0 - 63 table 1 - mode selection for backplane streams
data sheet MT90868 19 zarlink semiconductor inc. figure 7 - local output advancement timing diagram when the data rate is 8mb/s possible adjustment of the local input data streams, lsti0 - lsti63 is up to 7 3/4 bits. the resolution is 1/4 bit or 1/4 c8o cycle. for backplane, the possible ad justment of the input da ta streams, bsti0 - bst i63 is up to 7 3/4 bits with a resolution of 1/4 bit (or 1/8 c8 i clock cycle) when the input data rate is 16.384mb/s. when the input data rate is 32.768mb/s, the possible adjustment is up to 7 1/ 2 bits with a resolution of 1/2 bit (or 1/8 c8i clock cycle). figures 10, 11 and 12 describe the details of the input bit de lay programming for the local and the backplane interfaces respectively. figure 8 - backplane output advancement timing diagram when the data rate is 16mb/s fp8o bit 7 bit 6 lsto x bit advancement = 0 ch0 lsto x bit advancement = -1/8 (default) bit advancement, -1/8 c8o bit 7 bit 6 ch0 lsto x bit advancement = -1/4 bit advancement, -1/4 bit 7 bit 6 ch0 lsto x bit advancement = -3/8 bit advancement, -3/8 bit 7 bit 6 ch0 ch127 bit 0 ch127 bit 1 bit 0 ch127 bit 1 bit 0 bit 1 bit 1 bit 0 ch127 fp8i bit 7 bit 6 bsto x bit advancement = 0 ch0 bit 0 bsto x bit advancement = -1/4 ch255 bit advancement, -1/4 bit 1 bit 7 bit 6 ch0 bit 0 ch255 bit 1 bsto x bit advancement = -1/2 bit advancement, -1/2 bit 7 bit 6 ch0 bit 0 ch255 bit 1 (16.384mb/s) bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 2 bit 2 bit 2 (default) bsto x bit advancement = -3/4 bit advancement, -3/4 bit 7 bit 6 ch0 bit 0 ch255 bit 1 bit 5 bit 4 bit 2 c8i
MT90868 data sheet 20 zarlink semiconductor inc. figure 9 - backplane output advancement timing diagram when the data rate is 32mb/s figure 10 - local input bit delay timing diagram (the data rate is 8mb/s) fp8i bit 7 bit 6 bsto x bit advancement = 0 ch0 bit 0 bsto x bit advancement = -1/2 ch511 bit advancement, -1/2 bit 1 bit 7 bit 6 ch0 bit 0 ch511 bit 1 bsto x bit advancement = -1 bit advancement, -1 bit 7 bit 6 ch0 bit 0 ch511 bit 1 (32.768mb/s) bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 2 bit 2 bit 2 bit 3 bit 3 bit 3 bit 5 bit 5 bit 5 bit 3 bit 3 bit 3 bit 2 bit 2 bit 2 bit 1 bit 1 bit 1 bit 0 bit 0 bit 0 c8i (default) bsto x bit advancement = -1 1/2 bit advancement, -1 1/2 bit 7 bit 6 ch0 bit 0 ch511 bit 1 bit 5 bit 4 bit 4 bit 2 bit 3 bit 5 bit 3 bit 2 bit 1 bit 0 fp8o c8o 72 3 4 5 610 lsti x bit delay = 0 ch0 74 5 6 ch1 2 310 lsti x bit delay = 1/4 72 3 4 5 610 lsti x bit delay = 1 ch0 75 6 ch1 2 310 (default) 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 ch127 ch127 bit delay, 1/4 bit delay, 1 lsti x bit delay = 1/2 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 bit delay, 1/2 lsti x bit delay = 3/4 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch127 bit delay, 3/4 lsti x bit delay = 7 1/2 72 3 4 5 610 ch127 74 5 6 ch0 210 ch126 bit delay, 7 1/2 lsti x bit delay = 7 3/4 72 3 4 5 610 ch127 74 5 6 ch0 210 ch126 bit delay, 7 3/4
data sheet MT90868 21 zarlink semiconductor inc. figure 11 - backplane input bit delay timing diagram when the data rate is 16mb/s figure 12 - backplane input bit delay timing diagram when the data rate is 32mb/s 2.5 local input channel delay and local channel output advancement the MT90868 provides users with the capability of prog ramming the local input channel delay and the local output channel advancement. the local input channel delay programming allows all loca l input streams to have a different frame boundary with respect to the local frame pulse (f8o ). it is enabled when the licden bit in the control register (cr) is high. the local input channel delay registers (licdr0 - licdr31) allows the users to delay the input channel from 0 to 127 channel for every local input stream. figure 13 describes th e local channel delay timing with different delay values. the local output channel advancement programming allows all local output streams to have a different frame boundary with respect to the local frame pulse (f8o ). it is enabled when the locaen bit in the cr register is set to high. the local output channel advancement registers (locar0 - locar31) allows the users to advance the output channel from 0 to 127 channels for every local outp ut stream. figure 14 describes the local channel output advancement timing with different channel advancement values. 72 3 4 5 610 0 bstix (16mb/s) 1 2 3 4 5 610 7 ch1 ch 0 7 bit delay, 1/2 72 3 4 5 610 0 bstix bit delay = 1/2 1 2 3 4 5 610 7 ch1 ch0 7 bit delay = 0 default 72 3 4 5 610 0 bstix bit delay = 2 1 2 3 4 5 61 3 7 ch1 ch0 2 bit delay, 2 fp8i (8.192mhz) c8i (8khz) bstix (32mb/s) bstix bit delay = 1/2 bit delay = 0 default bstix bit delay = 1 72 3 4 5 610 ch0 72 3 4 5 610 ch1 2 310 72 3 4 5 610 ch3 2 3 4 5 610 ch2 7 72 3 4 5 610 ch0 72 3 4 5 610 ch1 2 310 72 3 4 5 610 ch3 2 3 4 5 610 ch2 7 bit delay, 1/2 72 3 4 5 610 ch0 72 3 4 5 610 ch1 2 310 72 3 4 5 61 ch3 2 3 4 5 610 ch2 7 bit delay, 1 4 fp8i (8.192mhz) c8i (8khz)
MT90868 data sheet 22 zarlink semiconductor inc. figure 13 - local input channel delay timing diagram figure 14 - local output channel advancement timing diagram 2.6 memory block programming the block programming register (bpr) provides users with the capability of initializing the local and backplane connection memories in two frames. the local connection memory is partitioned into local connection memory high (lcmh) and the local connection memory low (lcml). bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in bit 4 - bit 6 of the bpr register. bit 15 of every lcml location and bit 0 - bit 1 of every lcmh location will be programmed with the pattern stored in bits 1 to 3 of the bpr register. the other bit positions of the backplane connection memory, th e local connection memory low and all bits of the local connection memory high are loaded with zeros. see figure 15 for the connection memory contents when the device is in the block programming mode. the block programming mode is enabled by setting the memo ry block program (mbp) bit of the control register to fp8o c8o 72 3 4 5 610 channel delay = 0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 ch127 2 3 4 5 610 ch126 76 72 3 4 5 610 channel delay = 1 ch127 72 3 4 5 610 ch 0 2 310 72 3 4 5 610 ch126 2 3 4 5 610 ch125 76 72 3 4 5 610 channel delay = 2 ch126 72 3 4 5 610 ch127 2 310 72 3 4 5 610 ch125 2 3 4 5 610 ch0 76 (default) delay = 1 delay = 2 7 lsti x lsti x lsti x x = 0 to 63 note: fp8o c8o 72 3 4 5 610 lsto y channel advance =0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 ch127 2 3 4 5 610 ch126 76 72 3 4 5 610 lsto y channel advance = 1 ch1 72 3 4 5 610 ch2 2 310 72 3 4 5 610 ch0 2 3 4 5 610 ch127 76 72 3 4 5 610 lsto y channel advance = 2 ch2 72 3 4 5 610 ch3 2 310 72 3 4 5 610 ch1 2 3 4 5 610 ch0 76 (default) advance = 1 7 y = 0 to 63 note: advance = 2
data sheet MT90868 23 zarlink semiconductor inc. high. when the block programmi ng enable (bpe) bit of the bpr register is set to high, the block programming data will be loaded into bits 13 to 15 of every backplane connection memory location and bits 15 of every local connection memory low and bit 0 to bit 1 of every local connection memory high location. the other connection memory bits are loaded with zeros. it takes two frames (250 s) to allow the backplane and local connection memories to be loaded. upon the comp letion of the memory bl ock programming, the devi ce resets the bpe bit to low to indicating that the process is finished. see table 6 for the bit assignment of the bpr register. figure 15 - block programming data in the connection memories 76543210 8 9 10 11 12 13 0 14 15 bbpd2 bbpd 1 0000000000 bbpd0 0 0 backplane connection memory (bcm) 76543210 8 9 10 11 12 13 0 14 15 0 0000000000 0 0 0 local connection memory low (lcml) 76543210 8 9 10 11 12 13 0 14 15 0 0 00000000lbpd2 lbpd1 0 0 0 lbpd0 local connection memory high (lcmh)
MT90868 data sheet 24 zarlink semiconductor inc. 3.0 switching paths the MT90868 provides users with four switching paths, namely "backplane-to-local", "local-to-backplane", "backplane-to-backplane" and "local-to- local". the switching configuration is controlled by programming the local connection and the backplane connection memories. the "backplane-to-local" switching path allows the device to perform data switching between the backplane input port and the local output port among 32,768 backplane inpu t channels and 8,192 local output channels. the local connection memory determines the switching configur ations. see table 30 and table 31 for the details. the "local-to-backplane" switching path allows users to perform data switching between the local input port and the backplane output port among 8,192 local input channel s and 16,380 or 32,760 backplane output channels when operated in the 16mb/s or 32mb/s mode respectively. th e last channel (ch255 or ch511) of the backplane output streams bsto60 to bsto63 or bsto58 to bsto63 contains invalid output data for the 16mb/s or 32mb/s mode respectively. avoid using the last channel of these st reams for the "local-to-backp lane" data switching. the backplane connection memory determines the switching configurations. see table 32 for the details. the "local-to-local" switching path allows users to perform data switching between the local input and the local output ports among 8,192 local input and 8,192 local out put ports. the local connec tion memory determines the switching configurations. see table 30 and table 31 for the details. the "backplane-to-backplane" switching path allows users to perform data switching between the backplane input and the backplane output ports. in this switching mode, on ly two backplane input stream s can be selected by the backplane data input selection register (bdisr). the switching capacity is 512 x 512 or 1,024 x 1,024 backplane channels for the 16mb/s or 32mb/s mode respectively. the bdisr register selects two backplane input data streams, namely, stream a and stream b to support the "backplane-to-backplane" switching. the backplane connection memory determines the switching configurations. see table 33 for the details. 3.1 throughput delay the usage of the local input channel delay buffer and the local output channel advancement buffer affects the data throughput delay for the four data switching paths. the usage of these two buffers is controlled by the licden and the locaen bits in the control register (cr). when li cden and locaen bits are low, the "backplane-to-local" switching path has a throughput delay of one frame plus 2 channel slots; the "local-to-backplane", the "backplane- to-backplane" and the "local-to-local" switching paths have the throughput delay of two frames. switching path data delay input buffer** off output buffer** off (licden = 0) (locaen = 0) input buffer on output buffer off (licden = 1) (locaen = 0) input buffer off output buffer on (licden = 0) (locaen = 1) input buffer on output buffer on (licden = 1) (locaen = 1) local-to-backplane 2 frames 3 frames 2 frames 3 frames local-to-local 2 frames 3 frames 3 frames 4 frames backplane-to-local 1 frame + 2 ch 1 frame + 2 ch 2 frames + 2 ch 2 frames + 2 ch backplane-to-backplane 2 frames 2 frames 2 frames 2 frames ** note: input buffer = local input channel delay buffer output buffer = local output channel advancement buffer. table 2 - data delay through the device via different switching paths
data sheet MT90868 25 zarlink semiconductor inc. when the local input data streams pass through the local input channel delay buffer to perform the input channel adjustment by setting the licden bit to high, the device will add one more frame data to the "local-to-backplane" and the "local-to-local" data switchi ng paths. when the local output data streams pass through the local output channel advancement buffer to perform the output chan nel adjustment by setting the locaen bit to high, the device will add one more frame data delay to the "backp lane-to-local" and the "local-to-local" switching paths. table 2 describes the different delay throughput for the various data switching paths. 4.0 microprocessor interface the MT90868 provides a microprocessor port interface for non-multiplexed bus structures. this interface is compatible to motorola non-multiplexe d bus structure specification. the required microprocessor signals are the 16-bit parallel data bus (d15 - d0), 16-bit addre ss bus (a15 - a0) and four control lines (cs , ds , r/w and dta ). see figure 23 for details on the motorola non-multiplexed bus timing. the MT90868 synchronous microprocessor port provides a ccess to the internal registers, the connection and the data memories. all memory mapping lo cations are read/write accessible except the local and backplane bit error rate count registers (lbcr and bbcr) and data memories which can only be read by the users. 4.1 address mapping of registers and memories the address bus of the microprocessor port interface select s the internal registers and the memories. if the address bit, a15 is low, then the registers are addressed by a14 to a0 as shown in table 3. if a15 is high, the remaining address input lines are used to select the data and connection memory positions corresponding to the serial input or output data streams as shown in table 4.
MT90868 data sheet 26 zarlink semiconductor inc. a15-a0 internal register 0000 h control register, cr 0001 h block programming register, bpr 0002 h local input channel delay register 0, licdr0 0003 h local input channel delay register 1, licdr1 0004 h local input channel delay register 2, licdr2 0005 h local input channel delay register 3, licdr3 0006 h local input channel delay register 4, licdr4 0007 h local input channel delay register 5, licdr5 0008 h local input channel delay register 6, licdr6 0009 h local input channel delay register 7, licdr7 000a h local input channel delay register 8, licdr8 000b h local input channel delay register 9, licdr9 000c h local input channel delay register 10, licdr10 000d h local input channel delay register 11, licdr11 000e h local input channel delay register 12, licdr12 000f h local input channel delay register 13, licdr13 0010 h local input channel delay register 14, licdr14 0011 h local input channel delay register 15, licdr15 0012 h local input channel delay register 16, licdr16 0013 h local input channel delay register 17, licdr17 0014 h local input channel delay register 18, licdr18 0015 h local input channel delay register 19, licdr19 0016 h local input channel delay register 20, licdr20 0017 h local input channel delay register 21, licdr21 0018 h local input channel delay register 22, licdr22 0019 h local input channel delay register 23, licdr23 table 3 - address map for internal registers, when a15 = 0
data sheet MT90868 27 zarlink semiconductor inc. 001a h local input channel delay register 24, licdr24 001b h local input channel delay register 25, licdr25 001c h local input channel delay register 26, licdr26 001d h local input channel delay register 27, licdr27 001e h local input channel delay register 28, licdr28 001f h local input channel delay register 29, licdr29 0020 h local input channel delay register 30, licdr30 0021 h local input channel delay register 31, licdr31 0022 h local output channel advancement register 0, locar0 0023 h local output channel advancement register 1, locar1 0024 h local output channel advancement register 2, locar2 0025 h local output channel advancement register 3, locar3 0026 h local output channel advancement register 4, locar4 0027 h local output channel advancement register 5, locar5 0028 h local output channel advancement register 6, locar6 0029 h local output channel advancement register 7, locar7 002a h local output channel advancement register 8, locar8 002b h local output channel advancement register 9, locar9 002c h local output channel advancement register 10, locar10 002d h local output channel advancement register 11, locar11 002e h local output channel advancement register 12, locar12 002f h local output channel advancement register 13, locar13 0030 h local output channel advancement register 14, locar14 0031 h local output channel advancement register 15, locar15 0032 h local output channel advancement register 16, locar16 0033 h local output channel advancement register 17, locar17 a15-a0 internal register table 3 - address map for internal registers, when a15 = 0 (continued) 0034 h local output channel advancement register 18, locar18 0035 h local output channel advancement register 19, locar19 0036 h local output channel advancement register 20, locar20 0037 h local output channel advancement register 21, locar21 0038 h local output channel advancement register 22, locar22 0039 h local output channel advancement register 23, locar23 003a h local output channel advancement register 24, locar24 003b h local output channel advancement register 25, locar25 003c h local output channel advancement register 26, locar26 003d h local output channel advancement register 27, locar27 003e h local output channel advancement register 28, locar28 003f h local output channel advancement register 29, locar29 0040 h local output channel advancement register 30, locar30 0041 h local output channel advancement register 31, locar31 0042 h local input bit delay register 0, lidr0 0043 h local input bit delay register 1, lidr1 0044 h local input bit delay register 2, lidr2 0045 h local input bit delay register 3, lidr3 0046 h local input bit delay register 4, lidr4 0047 h local input bit delay register 5, lidr5 0048 h local input bit delay register 6, lidr6 0049 h local input bit delay register 7, lidr7 004a h local input bit delay register 8, lidr8 004b h local input bit delay register 9, lidr9 004c h local input bit delay register 10, lidr10 004d h local input bit delay register 11, lidr11 a15-a0 internal register table 3 - address map for internal registers, when a15 = 0 (continued) 004e h local input bit delay register 12, lidr12 004f h local input bit delay register 13, lidr13 0050 h local input bit delay register 14, lidr14 0051 h local input bit delay register 15, lidr15 0052 h local input bit delay register 16, lidr16 0053 h local input bit delay register 17, lidr17 0054 h local input bit delay register 18, lidr18 0055 h local input bit delay register 19, lidr19 0056 h local input bit delay register 20, lidr20 0057 h local input bit delay register 21, lidr21 0058 h backplane input bit delay register 0, bidr0 0059 h backplane input bit delay register 1, bidr1 005a h backplane input bit delay register 2, bidr2 005b h backplane input bit delay register 3, bidr3 005c h backplane input bit delay register 4, bidr4 005d h backplane input bit delay register 5, bidr5 005e h backplane input bit delay register 6, bidr6 005f h backplane input bit delay register 7, bidr7 0060 h backplane input bit delay register 8, bidr8 0061 h backplane input bit delay register 9, bidr9 0062 h backplane input bit delay register 10, bidr10 0063 h backplane input bit delay register 11, bidr11 0064 h backplane input bit delay register 12, bidr12 0065 h backplane input bit delay register 13, bidr13 0066 h backplane input bit delay register 14, bidr14 0067 h backplane input bit delay register 15, bidr15 a15-a0 internal register table 3 - address map for internal registers, when a15 = 0 (continued)
MT90868 data sheet 28 zarlink semiconductor inc. 0068 h backplane input bit delay register 16, bidr16 0069 h backplane input bit delay register 17, bidr17 006a h backplane input bit delay register 18, bidr18 006b h backplane input bit delay register 19, bidr19 006c h backplane input bit delay register 20, bidr20 006d h backplane input bit delay register 21, bidr21 006e h local output advancement register 0, loar0 006f h local output advancement register 1, loar1 0070 h local output advancement register 2, loar2 0071 h local output advancement register 3, loar3 0072 h local output advancement register 4, loar4 0073 h local output advancement register 5, loar5 0074 h local output advancement register 6, loar6 0075 h local output advancement register 7, loar7 0076 h backplane output advancement register 0, boar0 0077 h backplane output advancement register 1, boar1 0078 h backplane output advancement register 2, boar2 0079 h backplane output advancement register 3, boar3 007a h backplane output advancement register 4, boar4 007b h backplane output advancement register 5, boar5 007c h backplane output advancement register 6, boar6 007d h backplane output advancement register 7, boar7 007e h backplane data input selection register, bdisr 007f h backplane data memory read selection register, bdmrsr 0080 h local data memory read selection register, ldmrsr 0081 h local ber start receive register, lbsrr a15-a0 internal register table 3 - address map for internal registers, when a15 = 0 (continued) 0082 h local ber length register, lblr 0083 h local ber count register, lbcr 0084 h backplane ber start receive register, bbsrr 0085 h backplane ber length register, bblr 0086 h backplane ber count register, bbcr 0087 h reserved 7fff h reserved a15-a0 internal register table 3 - address map for internal registers, when a15 = 0 (continued)
data sheet MT90868 29 zarlink semiconductor inc. the control register (cr) and the block programming regi ster (bpr) control all the major functions of the device. the control register (cr) and the block programming register (bpr) should be programmed immediately after system power up to establish the desire d switching configur ation as explained in the frame a lignment timing and the switching configurations sections. the control register is used to select data or connec tion memory for microport op erations through the memory select bits. the register also enable s the local input channel delay, the output channel advancement, the backplane per-channel output tristate or per-channel driven-high co ntrol selection, the memory block programming mode and the ber test. the block programming regist er consists of the block programming data bits (lpbd2 - lpbd0, bbpd2 - bbpd0) and the block programming enable bit (bpe). the bpe bit allows users to program the entire backplane and local connection memories. see memory block programming section. the bpr register also controls the local and the backplane frame pulse polarities. 4.2 backplane connection memory the backplane connection memory (bcm) is 16-bit wide. it controls the switching configuration of the backplane interface through the backplane source control (bsrc) bit. w hen this bit is low, the input source is from the local input port and the "local-to-backplane" switching paths can be configured. when this bit is high, the input source is from the backplane input port and the "backplane-to-ba ckplane" switching paths can be configured. locations in the backplane connection memory are associated with particular bsto streams. the btm1 - btm0 bits of each backplane connection memory determine the per-channel tristate (or driven-high) a15 (note 1) stream address (stream 0 - 63) channel address (channel 0 - 511) a 14 a 13 a 12 a 11 a 10 a 9 stream # a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 channel # 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 0 0 0 0 . . . . . . 0 0 0 1 1 1 1 1 . . . . . . 1 1 1 1 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 0 . . . . . . 1 1 1 1 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 0 . . . . . . 1 1 1 1 0 0 0 0 . . . . . . 1 1 1 0 0 0 0 1 . . . . . . 1 1 1 1 0 0 1 1 . . . . . . 0 1 1 0 0 1 1 0 . . . . . . 0 0 1 1 0 1 0 1 . . . . . . 1 0 1 0 1 0 1 0 . . . . . . 0 1 0 1 stream 0, c or e (note 5) stream 1, d or f (note 5) stream 2 stream 3 . . . . . . . stream 29 stream 30 stream 31 stream 32 stream 33 stream 34 stream 35 stream 36 . . . . . . stream 60 stream 61 stream 62 stream 63 0 0 0 0 . . . 0 0 0 0 0 0 0 0 . . . 0 0 0 0 1 1 . . . 1 1 0 0 0 0 . . . 0 0 0 0 1 1 1 1 . . . 1 1 1 1 0 0 . . . 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 0 1 1 0 0 . . . 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 . . . 1 1 0 0 1 1 . . . 0 0 1 1 0 0 1 1 . . . 0 0 1 1 0 0 . . . 1 1 0 1 0 1 . . . 0 1 0 1 0 1 0 1 . . . 0 1 0 1 0 1 . . . 0 1 ch 0 ch 1 ch 2 ch 3 . . . ch 124 ch 125 ch 126 ch 127 (note 2) ch 128 ch 129 ch 130 ch 131 . . . ch 252 ch 253 ch 254 ch 255 (note 3) ch 256 ch 257 . . . ch 510 ch 511 (note 4) notes: 1. bit a15 must be high to access the data memory and connection memory positions. (a15 must be low to access registers.) 2. channels 0 to 127 are used when serial stream is at 8.192mb/s. 3. channels 0 to 255 are used when serial stream is at 16.384mb/s. 4. channels 0 to 511 are used when serial stream is at 32.768mb/s. 5. stream c&d or stream e&f are selected by the backplane data memory read selection register (bdmrsr) or the local data memory read selection register (ldmrsr) respectively. these streams are selected to support the microprocessor port data memory read operat ion. table 4 - address map for memory locations, when a15 = 1
MT90868 data sheet 30 zarlink semiconductor inc. control and the per-channel message and the normal modes. in the switching mode, the contents of the backp lane connection memo ry stream address bits (bsab0 - bsab5) and channel address bits (bcab0 - bcab6) define the source information (stream and channel) of the time slot that will be switched to the backplane bsto streams. during the message mode, only the lower 8 least significant bits of the backplane connection memory will be transferred to the bsto pins. 4.3 local connection memory the local connection memory controls the local interface switching configurations thr ough the local mode selection control (lmsc) bit. when this bit is low, the input source is from the backplane input port and the "backplane-to- local" switching path can be configured. when it is high, th e input source is from the local input port and the "local- to-local" switching path can be configured. the local connection memory consists of two parts, namely, the local connection memory low (lcml) and the local connection memory high (lcmh). each of them is 16-bit wide. locations in the local connection memory are associated with particular lsto output streams. the ltm1 - ltm0 bits of each local connection memory high (lcmh) determine the per-channel message mode, the pre-channel tristate and the normal modes. in the switching mode, the stream ad dress bits (lsab0 - lsab5) and channel address bits (lcab0 - lcab8) of the local connection memory low (lcml) define the source info rmation (stream and channel) of the time slot that will be switched to the local lsto streams. during the message mode , only the lower 8 least significant bits of the local connection memory low are transferred to the lsto pins. 4.4 data memory read operation all connection memory content can be read from the mi croprocessor port. however, only limited data memory contents can be read from the micro- processor port at any one time. the backplane data memory has 1,024 locations and the local data memory has 256 locations to support th e data memory reads. the backplane data memory read selection register (bdmrsr) selects the two backplane input streams which will be read (or monitored) from the microprocessor po rt. the selected backplane input streams are labelled as stream c and stream d. the local data memory read se lection register (ldmrsr) selects the two local input streams which will be read (or monitored) from the micr oprocessor port. the selected backplane input streams are labelled as stream e and stream f. users need to program the bdmrsr and ldmrsr registers before the proper data memory read operations can occur. see tables 22 and 23 for the description of the me mory read selection register s. also, see table 4 for the microprocessor addresses required to access stream c&d or stream e&f. refer to the ms0 - 2 bits in the control registers for the selection of the data memory to be read from the microprocessor port. 4.5 data transfer acknowledge the dta pin of the microprocessor is driven low by the internal logi c to indicate that a da ta bus transfer cycle is completed. when the bus cycle is ende d, the dta switches to the high impedance state. an external pull-up is required at this output. 4.6 local external tristate control the MT90868 allows users the flexibility to perform the pe r-channel tristate operation for the local interface when external drivers or buffers are used for the lsto0-64 outputs. the device provides four output control signals, lcsto0 - lcsto3 which have the data rate of 16.384mb/s with 8,192 control bits per frame. each control bit position is corresponding to a specific output stream and channel location as defined in the local connection memory. when the ltm0 and ltm1 bits in the lcmh are programmed to tristate selected local output channels, the corresponding lcsto control bits will set to high for the selected
data sheet MT90868 31 zarlink semiconductor inc. tristate output channels. for example, if we program ch annel 0 of the lsto4 to be tristated, the control bit lsto4_ch0 will set to high. with the local output channel advancement feature disa bled, the lcsto0 output is advanced by nine c8o cycles from the frame boundary to send out the control bit for the channel 0 of the lsto0 stream. similarly, the lcsto1, lcsto2 and lcsto3 outputs are advanced by nine c8o cycles for the channel 0 of the lsto1; lsto2 and lsto3 output streams respectively. the advan cement in the lcsto streams allows the external drivers or buffers to process the lcsto control bits accordingly before the actual lsto data is output from the device. figure 16 - local external tristate control timing when the local output channel advancement feature is enabled, lcsto signals for those advanced output channels will also be advanced together with the actual channel out puts. figure 16 describes the local external tristate control timing. the ode and reset pins also control the lcsto pins. see table 5, the osb bit description in the control register. 4.7 bit error rate test the MT90868 offers users the bit error rate (ber) test feature for the backpla ne and local interfaces. the circuitry of the ber test consists of a transmitter and a receiver on both interfaces which can transmit and receive the ber patterns independently. the transmitter can ou tput pseudo random patterns of the form 2 15 - 1 which can start anywhere in the frame and last a minimum of one channel and a maximum of one frame time (125 s). the ber test mode is activated by setting the ltm1 - ltm0 bits to "11" or the btm1 - btm0 bits to "11" in the local and the 76 lsto0 ch 0 ch 126 1 2 30 ch127 5 64 lsto63 lcsto0 lsto60,ch0 lsto56,ch0 lsto52,ch0 lsto48,ch0 lsto44,ch0 lsto40,ch0 lsto36,ch0 lsto32,ch0 lsto28,ch0 lsto24,ch0 lsto20,ch0 lsto16,ch0 l s t o 8 , c h 1 lsto4,ch1 lsto0,ch1 lsto60,ch127 lsto56,ch127 lsto52,ch127 lsto48,ch127 lsto44,ch127 lsto40,ch127 lsto36,ch127 lsto32,ch127 lsto28,ch127 l s t o 8 , c h 0 lsto4,ch0 lsto0,ch0 l s t o 1 2 , c h 0 lsto60,ch0 lsto56,ch0 l s t o 8 , c h 1 lsto4,ch1 lsto0,ch1 l s t o 1 2 , c h 1 ch127 7 lsto24,ch127 lsto20,ch1 nine c8o cycles 1 2 30 54 10 7 76 ch 0 1 2 30 5 64 ch127 7 1 2 30 54 10 7 ch 126 ch127 l s t o 1 6 , c h 1 l s t 1 2 , c h 1 l s t 1 6 , c h 1 lcsto1 lsto61,ch0 lsto57,ch0 lsto53,ch0 lsto49,ch0 lsto45,ch0 lsto41,ch0 lsto37,ch0 lsto33,ch0 lsto29,ch0 lsto25ch0 lsto21,ch0 lsto17,ch0 l s t o 9 , c h 1 lsto5,ch1 lsto1,ch1 lsto61,ch127 lsto57,ch127 lsto53,ch127 lsto49,ch127 lsto45,ch127 lsto41,ch127 lsto37,ch127 lsto33,ch127 lsto29,ch127 l s t o 9 , c h 0 lsto5,ch0 lsto1,ch0 l s t o 1 3 , c h 0 lsto61,ch0 lsto57,ch0 l s t o 9 , c h 1 lsto5,ch1 lsto1,ch1 l s t o 1 3 , c h 1 lsto25,ch127 lsto21,ch1 l s t o 1 7 , c h 1 l s t o 1 3 , c h 1 l s t o 1 7 , c h 1 fp8o c8o lcsto2 lsto62,ch0 lsto58,ch0 lsto54,ch0 lsto50,ch0 lsto46,ch0 lsto42,ch0 lsto38,ch0 lsto34,ch0 lsto30,ch0 lsto26,ch0 lsto22,ch0 lsto18,ch0 l s t o 1 0 , c h 1 lsto6,ch1 lsto2,ch1 lsto62,ch127 lsto58,ch127 lsto54,ch127 lsto50,ch127 lsto46,ch127 lsto42,ch127 lsto38,ch127 lsto34,ch127 lsto30,ch127 l s t o 1 0 , c h 0 lsto6,ch0 lsto2,ch0 l s t o 1 4 , c h 0 lsto62,ch0 lsto58,ch0 l s t o 1 0 , c h 1 lsto6,ch1 lsto2,ch1 l s t o 1 4 , c h 1 lsto26,ch127 lsto22,ch1 l s t o 1 8 , c h 1 l s t o 1 4 , c h 1 l s t o 1 8 , c h 1 lcsto3 lsto63,ch0 lsto59,ch0 lsto55,ch0 lsto51,ch0 lsto47,ch0 lsto43,ch0 lsto39,ch0 lsto35,ch0 lsto31,ch0 lsto27,ch0 lsto23,ch0 lsto19,ch0 l s t o 1 1 , c h 1 lsto7,ch1 lsto3,ch1 lsto63,ch127 lsto59,ch127 lsto55,ch127 lsto51,ch127 lsto47,ch127 lsto43,ch127 lsto39,ch127 lsto35,ch127 lsto31,ch127 l s t o 1 1 , c h 0 lsto7,ch0 lsto3,ch0 l s t o 1 5 , c h 0 lsto63,ch0 lsto59,ch0 l s t o 1 1 , c h 1 lsto7,ch1 lsto3,ch1 l s t o 1 5 , c h 1 lsto27,ch127 lsto23,ch1 l s t o 1 9 , c h 1 l s t o 1 5 , c h 1 l s t o 1 9 , c h 1
MT90868 data sheet 32 zarlink semiconductor inc. backplane connecti on memory respectively and al so setting the sberl bit (for local) or the sberb bit (for backplane) in the control register (cr) to high. for the test, the users can program the ber pattern for mult iple consecutive output channels through the connection memory. however, the number of consecutive output ch annels must be the same as the number of input channels defined in the local and backplane ber length registers (lblr and bblr) which define how many ber channels to be monitored by the ber receivers. there are three types of registers to control the ber transmitter and receiver circuits. the ber start receive registers for the local (lbsrr) and th e backplane (bbsrr) define the input stream and channel from where the ber sequence will start to compare. the ber length re gisters for the local (lblr) and the backplane (bblr) define the number of input channels which the sequence will be last. the ber count registers for the local (lbcr) and the backplane (bbcr) contain the number of counted ber errors after the comparison. to prevent overflow, the internal ber counter will stop updating the error count when the error count reaches 0xffff. in additional to the ber registers, the cberl bit and the cberb bit of t he control register are used to clear the backplane and the local bit error count registers; the sberb and sberl are us ed to enable the back plane and the local ber transmitters and receivers. see table 24, 25, 26, 27, 28 a nd 29 for the detailed descriptions of the ber registers. the ber test should be carried out as follows: ? set the sberb and the sberl bits to zero to disable the backplane and the local ber transmi tters during the programming of the backplane and local connection memories for the ber test; when the ber transmitters are disabled, the tr ansmitter outputs are set to zero, ? set the sberb and sberl bit from ze ro to one to enable the ber tran smitters and rece ivers upon the completion of the programming of the connection memories, ? allow the ber transmitters and receivers to run for at least two frames (or the delay between the serial data output and the serial date input) before the ber receivers can correctly identify errors in the ber pattern but ignore the error counts displayed in the ber count registers during this training period, ? after the training period, clear the ber count registers by setting the cberl and the cberb bit of the control register from zero to one, ? set the cberl and cberb bits from one to zero to release the ber counter; the ber receivers receive the ber sequence and perform the comparison, ? record the bit errors by reading the ber count registers upon the completion of the ber test, ? clear the ber counters by settin g the cberb and cberl from zero to one upon the completion of the ber test, (note : the transmitter and receiver for both local and backplane interface can be controlled independently to each other.) figure 17 - backplane output streams ava ilability for ber test at 32mb/s mode when the backplane port is in the 32mb/s mode, the bit error rate test mode is not available for the backplane output streams bsto0, 1, 4, 5, 8, 9, ... , , unless the output stream or (for ) is enabled for the ber test mode. figure 17 explains the details. when the backplane port is in the 16mb/s mode, all backplane output streams are available. bsto 0, 2, 8, 10, 4, 6, 12, 56, 58, 60, ... , 62. bsto 1, 3, 9, 11, 5, 7, 13, 57, 59, 61, ... , 63. to enable the bit error rate test for the unshaded channels, one of the shaded channels on their right hand side has to be enabled. the bit error rate test mode is available for the shaded channels. example: to enable ch8 for ber test mode, ch10 or ch11 has to be enabled. 4 n 0 +4 n 1 +4 n 2 +4 n 3 +0 n 15 ?
data sheet MT90868 33 zarlink semiconductor inc. 4.8 device initialization the reset pin is a synchronous system rese t signal that puts the MT90868 into its reset state. when reset goes low, it disables the lsto0-63 and lcsto0-3 outputs and drives the bsto0-63 outputs to high. it also clears the internal device registers and the internal counters. see figure 25 for the reset timing. upon powering up, the MT90868 must be initialized according to the following initialization sequences: ? set the ode pin to low to tristate the lsto0- 63, lcsto0-3 and bsto0-63 outputs. ? set the trst pin to low to disable the internal jtag tap controller, ? set reset pin to low to reset the device, to ensure proper reset action, the reset pin must be held low for longer than 500ns. a delay of 100 s must also be applied before the first microprocessor access is performed after the reset pin is set high, this delay is requi red for the initialization of the apll. ? use the block programming mode as described in the memory block programming section to initialize the local and the backplane connection memories, ? set the ode pin to high after the connection memories are programmed to release the tristate on lsto0- 63, lcsto0-3 and bsto)-63 outputs. ? set bit 11, stby, of the control register (cr) to high for normal functional mode. 4.9 jtag support the MT90868 jtag interface confo rms to the boundary-scan ieee1149. 1 standard. the op eration of the boundary-scan circuitry is controlled by an external test access port (tap) controller. see figure 24 for the jtag test port timing. 4.9.1 test access port (tap) the test access port (tap) a ccesses the MT90868 test functi ons. it consists of four input pins and one output pin as follows: ? test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remains independent in the functional mode. the tck pe rmits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. ? test mode select input (tms) the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vdd when it is not driven from an external source. ? test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vdd when it is not driven from an external source. ? test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) it resets the jtag scan struct ure. this pin is internally pulled to vdd when it is no t driven from an external source.
MT90868 data sheet 34 zarlink semiconductor inc. 4.9.2 instruction register the MT90868 uses the pu blic instructions defined in the ieee 1149.1 standard . the jtag interfac e contains a four- bit instruction register. inst ructions are serially loaded into the instru ction register from the tdi when the tap controller is in its shifted-ir state. these instructions are subsequently de coded to achieve two basic functions: to select the test data register that may operate while the instruction is current an d to define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. 4.9.3 test data register as specified in ieee 11 49.1, the MT90868 jtag interface contains thre e test data registers: ? the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the MT90868 core logic. ? the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. ? the device identification register the jtag device id for the MT90868 is 0086814bh. version<31:28>: 0000 part no. <27:12>: 0000 1000 0110 1000 manufacturer id<11:1>: 0001 0100 101 lsb<0>: 1 4.9.4 bsdl a bsdl (boundary scan description language) file is available from zarlink semiconductor to support the use of the ieee 1149 te st interface. bit name description 15 bhiz backplane tristate or driven-high control: when this bit is low, the backplane outputs support the per-channel tristate feature. wh en this bit is high, the backplane outputs support the per-channel driven high feature. 14 locaen local output channel advancement enable: when this bit is high, the local output channel advancement is enabled and the local output data will pass through the local output channel advancement buffer as shown in figure 1. the local output channel advancement registers (locar31 - locar0) control the channel advancement from 0 to 127 channels. when this bit is low, the channel advancement is disabled (default condition) and the local output data will bypass the local output channel advancement buffer. 13 licden local input channel delay enable: when this bit is high, the local input channel advancement is enabled and the local input data will pass through the local input channel delay buffer as shown in figure 1. the local input channel delay registers (licdr31 - licdr0) control the channel delay from 0 to 127 channels. when this bit is low, the channel delay is disabled (default condition) and the local input data will bypass the local input channel delay buffer. table 5 - control register (cr) bits read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bhiz locaen licden 0 stby prst cberb sberb cberl sberl bms mbp osb ms2 ms1 ms0
data sheet MT90868 35 zarlink semiconductor inc. 12 unused reserved. in normal functional mode, this bit must be set to zero . 11 stby standby: in normal functional mode, this bit must be set to one after power up. 10 prst prbs reset: when this bit is high, the output of the ber transmitter will be initialized. 9 cberb backplane bit error rate clear: when this bit is high, it resets the backplane internal bit error counter and the content of the backplane bit error count register (bbcr) to zero. upon completion of the reset, set this bit to zero. 8 sberb backplane bit error rate test start: when this bit is high, it enables the backplane ber transmitter and receiver; starts the backplane bit error rate test. the bit error test result is kept in the backplane bit error count (bbcr) register. upon the completion of the ber test, set this bit to zero. 7 cberl local bit error rate clear: when this bit is high, it resets the local internal bit error counter and the content of the local bit er ror count register (lbcr) to zero. upon completion of the reset, set this bit to zero. 6 sberl local start bit er ror rate test: when this bit is high, it enables the local ber transmitter and receiver; starts the local bit erro r rate test. the bit erro r test result is kept in the local bit error count (lbcr) register. upon the completion of the ber test, set this bit to zero. 5bms backplane mode select: when the bime pin is low and this bit is low, it enables the 16mb/s mode and bsti0-63 and bsto0-63 have data rate of 16.384mb/s. when the bime pin is low and this bit is high, it enables the 32mb/s mode and bsti0-63 and bsto0-63 have data rate of 32.768mb/s. when the bime pin is high, set this bit to high to enable the bit interleaving mode operation. 4mbp memory block programming: when this bit is high, the connection memory block programming mode is enabled to program bit 15 of the local connection memory low, bit 0 and bit 1 of the local connection memory high and bit 13 to bit 15 of the backplane connection memory. when it is low, the memory block programming mode is disabled. refer to figure 15 for details. bit name description table 5 - control register (cr) bits (continued) read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bhiz locaen licden 0 stby prst cberb sberb cberl sberl bms mbp osb ms2 ms1 ms0
MT90868 data sheet 36 zarlink semiconductor inc. 3osb output stand by bit: this bit enables the bsto0 - bstoo63 and the lsto0 - lsto63 serial outputs. the following table describes the hiz control of the serial data outputs: 2 - 0 ms2 - 0 memory select bit: these three bits are used to select different connection and data memories: 000, local connection memory low (lcml) is selected for read or write operations. 001, local connection memory high (lcmh) is selected for read or write operations. 010, backplane connection memory (bcm) is selected for read or write operations. 011, local data memory is selected for read operation; streams e and f are selected by the ldmrsr register can be read. 100, backplane data memory is selected for read operation; streams c and d are selected by the bdmrsr registers can be read. bit name description table 5 - control register (cr) bits (continued) read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bhiz locaen licden 0 stby prst cberb sberb cberl sberl bms mbp osb ms2 ms1 ms0 bime pin reset pin ode pin osb bit bhiz bit lsto0 to lsto63 bsto0 to bsto63 lcsto0 to lcsto3 1 0 x x x hiz driven high driven high 1 1 0 x x hiz driven high driven high 1 1 1 0 x hiz driven high driven high 1 1 1 1 x active active active 0 0 x x x hiz hiz driven high 0 1 0 x 0 hiz hiz driven high 0 1 0 x 1 hiz driven high driven high 0 1 1 0 0 hiz hiz driven high 0 1 101 hiz driven high driven high 0 1 1 1 x active active active
data sheet MT90868 37 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 lc8c local 8m output (c8o ) polarity control: when this bit is low, the c8o falling edge aligns with the frame boundary. when it is high, the c8o rising edge aligns with the frame boundary. 10 bfp8c backplane frame pulse (fp8i ) polarity control: when this bit is low, the input frame pulse should have the negative frame pulse format; the frame pulse goes low for 122ns at the frame boundary. when it is high, the input frame pulse should have the positive frame pulse format; the frame pulse goes high for 122ns at the frame boundary. 9 lfp16c local frame pulse (fp16o ) polarity control : when this bit is low, the output frame pulse has the negative frame pulse format. the frame pulse goes low for 61ns at the frame boundary. when it is high, the output frame pulse has the positive frame pulse format. the frame pulse goes high for 61ns at the frame boundary. 8lfp8c local frame pulse (fp8o ) polarity control: when this bit is low, the output frame pulse has the negative frame pulse format. the frame pulse goes low for 122ns at the frame boundary. when it is high, the output frame pulse has the positive frame pulse format. the frame pulse goes high for 122ns at the frame boundary. 7lfp4c local frame pulse (fp4o ) polarity control: when this bit is low, the output frame pulse has the negative frame pulse format. the frame pulse goes low for 244ns at the frame boundary. when it is high, the output frame pulse has the positive frame pulse format. the frame pulse goes high for 244ns at the frame boundary. 6 - 4 bbpd2 - 0 backplane block programming data: these bits refer to the value to be loaded into the backplane connection memory (bcm) whenever the memory block programming feature is activated. after the mbp bit in th e control register is set to high and the bpe bit is set to high, the contents of the bits bbpd2-0 are loaded into bit 13 to bit 15 of the bcm. bit 0-12 of the bcm are zeroed. 3 - 1 lbpd2 - 0 local block programming data: these bits refer to the value to be loaded into the local connection memory, i.e. local connection memory low (lcml) and local connection memory high (lcmh), whenever the memory block programming feature is activated. after the mbp bit in the contro l register is set to high and the bpe bit is set to high, the contents of the bits lbpd0 is loaded into bit 15 of the lcml and the lbpd1 to lbpd2 are loaded into bit 0 to bit 1 of the lcmh. bit 0 to bit 14 of lcml and bit 2 to bit 14 of lcmh are zeroed. 0 bpe block programming enable.: a zero to one transition of this bit enables the memory block programming function. the bpe, lbpd2-0 and bbpd2-0 bits in the bpr register must be defined in the same write operation. on ce the bpe bit is set to high, the device requires two frames to complete the block programming. after the programming function has fini shed, the bpe bit returns to lo w indicating the operation is completed. when the bpe is high, the bpe or mbp can be set to low to abort the programming operation. when bpe is high, the other bits in the bpr register must not be changed for two frames to ensure a proper block programming operation. whenever the microprocessor writes a one to the bpe bit, the block programming function is started, the user must maintain the same logical value to the other bits in the bpr register to avoid any change in the device setting. table 6 - block programming register (bpr) bits read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000lc8cbfp 8c lfp 16c lfp 8c lfp 4c bbpd 2 bbpd 1 bbpd 0 lbpd 2 lbpd 1 lbpd 0 bpe
MT90868 data sheet 38 zarlink semiconductor inc. name description licdx6 - licdx0 (see note 1) local input channel delay bits 6 - 0: the binary value of these seven bits defines the local input channel delay of the local data inputs. the input channel delay can be selected from ch0 to ch127 away from the local frame boundary. the local input channel offset delay value is only valid when the licden bit is high in the control register. note 1: x denotes a lsti stream number from 0 to 31. table 7 - local input channel delay registers (licdr0 to licdr15) read/write address: 0002 h - 00011 h reset value: 0000 h 1514131211109876543210 licdr0 0 licd 16 licd 15 licd 14 licd 13 licd 12 licd 11 licd 10 0 licd 06 licd 05 licd 04 licd 03 licd 02 licd 01 licd 00 licdr1 0 licd 36 licd 35 licd 34 licd 33 licd 32 licd 31 licd 30 0 licd 26 licd 25 licd 24 licd 23 licd 22 licd 21 licd 20 licdr2 0 licd 56 licd 55 licd 54 licd 53 licd 52 licd 51 licd 50 0 licd 46 licd 45 licd 44 licd 43 licd 42 licd 41 licd 40 licdr3 0 licd 76 licd 75 licd 74 licd 73 licd 72 licd 71 licd 70 0 licd 66 licd 65 licd 64 licd 63 licd 62 licd 61 licd 60 licdr4 0 licd 96 licd 95 licd 94 licd 93 licd 92 licd 91 licd 90 0 licd 86 licd 85 licd 84 licd 83 licd 82 licd 81 licd 80 licdr5 0 licd 116 licd 115 licd 114 licd 113 licd 112 licd 111 licd 110 0 licd 106 licd 105 licd 104 licd 103 licd 102 licd 101 licd 100 licdr6 0 licd 136 licd 135 licd 134 licd 133 licd 132 licd 131 licd 130 0 licd 126 licd 125 licd 124 licd 123 licd 122 licd 121 licd 120 licdr7 0 licd 156 licd 155 licd 154 licd 153 licd 152 licd 151 licd 150 0 licd 146 licd 145 licd 144 licd 143 licd 142 licd 141 licd 140 licdr8 0 licd 176 licd 175 licd 174 licd 173 licd 172 licd 171 licd 170 0 licd 166 licd 165 licd 164 licd 163 licd 162 licd 161 licd 160 licdr9 0 licd 196 licd 195 licd 194 licd 193 licd 192 licd 191 licd 190 0 licd 186 licd 185 licd 184 licd 183 licd 182 licd 181 licd 180 licdr10 0 licd 216 licd 215 licd 214 licd 213 licd 212 licd 211 licd 210 0 licd 206 licd 205 licd 204 licd 203 licd 202 licd 201 licd 200 licdr11 0 licd 236 licd 235 licd 234 licd 233 licd 232 licd 231 licd 230 0 licd 226 licd 225 licd 224 licd 223 licd 222 licd 221 licd 220 licdr12 0 licd 256 licd 255 licd 254 licd 253 licd 252 licd 251 licd 250 0 licd 246 licd 245 licd 244 licd 243 licd 242 licd 241 licd 240 licdr13 0 licd 276 licd 275 licd 274 licd 273 licd 272 licd 271 licd 270 0 licd 266 licd 265 licd 264 licd 263 licd 262 licd 261 licd 260 licdr14 0 licd 296 licd 295 licd 294 licd 293 licd 292 licd 291 licd 290 0 licd 286 licd 285 licd 284 licd 283 licd 282 licd 281 licd 280 licdr15 0 licd 316 licd 315 licd 314 licd 313 licd 312 licd 311 licd 310 0 licd 306 licd 305 licd 304 licd 303 licd 302 licd 301 licd 300
data sheet MT90868 39 zarlink semiconductor inc. name description licdy6 - licdy0 (see note 1) local input channel delay bits 6 - 0: the binary value of these seven bits defines the local input channel delay of the local data inputs. the input channel delay can be selected from ch0 to ch127 away from the local frame boundary. the local input channel offset delay value is only valid when the licden bit is high in the control register. note 1: y denotes a lsti stream number from 32 to 63. table 8 - local input channel delay registers (licdr16 to licdr31) read/write address: 0012 h - 00021 h reset value: 0000 h 1514131211109876543210 licdr16 0 licd 336 licd 335 licd 334 licd 333 licd 332 licd 331 licd 330 0 licd 326 licd 325 licd 324 licd 323 licd 322 licd 321 licd 320 licdr17 0 licd 356 licd 355 licd 354 licd 353 licd 352 licd 351 licd 350 0 licd 346 licd 345 licd 344 licd 343 licd 342 licd 341 licd 340 licdr18 0 licd 376 licd 375 licd 374 licd 373 licd 372 licd 371 licd 370 0 licd 366 licd 365 licd 364 licd 363 licd 362 licd 361 licd 360 licdr19 0 licd 396 licd 395 licd 394 licd 393 licd 392 licd 391 licd 390 0 licd 386 licd 385 licd 384 licd 383 licd 382 licd 381 licd 380 licdr20 0 licd 416 licd 415 licd 414 licd 413 licd 412 licd 411 licd 410 0 licd 406 licd 405 licd 404 licd 403 licd 402 licd 401 licd 400 licdr21 0 licd 436 licd 435 licd 434 licd 433 licd 432 licd 431 licd 430 0 licd 426 licd 425 licd 424 licd 423 licd 422 licd 421 licd 420 licdr22 0 licd 456 licd 455 licd 454 licd 453 licd 452 licd 451 licd 450 0 licd 446 licd 445 licd 444 licd 443 licd 442 licd 441 licd 440 licdr23 0 licd 476 licd 475 licd 474 licd 473 licd 472 licd 471 licd 470 0 licd 466 licd 465 licd 464 licd 463 licd 462 licd 461 licd 460 licdr24 0 licd 496 licd 495 licd 494 licd 493 licd 492 licd 491 licd 490 0 licd 486 licd 485 licd 484 licd 483 licd 482 licd 481 licd 480 licdr25 0 licd 516 licd 515 licd 514 licd 513 licd 512 licd 511 licd 510 0 licd 506 licd 505 licd 504 licd 503 licd 502 licd 501 licd 500 licdr26 0 licd 536 licd 535 licd 534 licd 533 licd 532 licd 531 licd 530 0 licd 526 licd 525 licd 524 licd 523 licd 522 licd 521 licd 520 licdr27 0 licd 556 licd 555 licd 554 licd 553 licd 552 licd 551 licd 550 0 licd 546 licd 545 licd 544 licd 543 licd 542 licd 541 licd 540 licdr28 0 licd 576 licd 575 licd 574 licd 573 licd 572 licd 571 licd 570 0 licd 566 licd 565 licd 564 licd 563 licd 562 licd 561 licd 560 licdr29 0 licd 596 licd 595 licd 594 licd 593 licd 592 licd 591 licd 590 0 licd 586 licd 585 licd 584 licd 583 licd 582 licd 581 licd 580 licdr30 0 licd 616 licd 615 licd 614 licd 613 licd 612 licd 611 licd 610 0 licd 606 licd 605 licd 604 licd 603 licd 602 licd 601 licd 600 licdr31 0 licd 636 licd 635 licd 634 licd 633 licd 632 licd 631 licd 630 0 licd 626 licd 625 licd 624 licd 623 licd 622 licd 621 licd 620
MT90868 data sheet 40 zarlink semiconductor inc. name description locax6 - locax0 (see note 1) local output channel advancement bits 6 - 0: the binary value of these seven bits defines the local output channel advancement of the local data outputs. the output channel advancement can be selected from ch0 to ch127 before the local frame boundary. the local output channel advancement value is only valid when the locaen bit is high in the control register. note 1: x denotes a lsto stream number from 0 to 31. table 9 - local output channel advan cement registers (locar0 to locar16) read/write address: 0022 h - 00031 h reset value: 0000 h 1514131211109876543210 locar0 0 loca 16 loca 15 loca 14 loca 13 loca 12 loca 11 loca 10 0 loca 06 loca 05 loca 04 loca 03 loca 02 loca 01 loca 00 locar1 0 loca 36 loca 35 loca 34 loca 33 loca 32 loca 31 loca 30 0 loca 26 loca 25 loca 24 loca 23 loca 22 loca 21 loca 20 locar2 0 loca 56 loca 55 loca 54 loca 53 loca 52 loca 51 loca 50 0 loca 46 loca 45 loca 44 loca 43 loca 42 loca 41 loca 40 locar3 0 loca 76 loca 75 loca 74 loca 73 loca 72 loca 71 loca 70 0 loca 66 loca 65 loca 64 loca 63 loca 62 loca 61 loca 60 locar4 0 loca 96 loca 95 loca 94 loca 93 loca 92 loca 91 loca 90 0 loca 86 loca 85 loca 84 loca 83 loca 82 loca 81 loca 80 locar5 0 loca 116 loca 115 loca 114 loca 113 loca 112 loca 111 loca 110 0 loca 106 loca 105 loca 104 loca 103 loca 102 loca 101 loca 100 locar6 0 loca 136 loca 135 loca 134 loca 133 loca 132 loca 131 loca 130 0 loca 126 loca 125 loca 124 loca 123 loca 122 loca 121 loca 120 locar7 0 loca 156 loca 155 loca 154 loca 153 loca 152 loca 151 loca 150 0 loca 146 loca 145 loca 144 loca 143 loca 142 loca 141 loca 140 locar8 0 loca 176 loca 175 loca 174 loca 173 loca 172 loca 171 loca 170 0 loca 166 loca 165 loca 164 loca 163 loca 162 loca 161 loca 160 locar9 0 loca 196 loca 195 loca 194 loca 193 loca 192 loca 191 loca 190 0 loca 186 loca 185 loca 184 loca 183 loca 182 loca 181 loca 180 locar10 0 loca 216 loca 215 loca 214 loca 213 loca 212 loca 211 loca 210 0 loca 206 loca 205 loca 204 loca 203 loca 202 loca 201 loca 200 locar11 0 loca 236 loca 235 loca 234 loca 233 loca 232 loca 231 loca 230 0 loca 226 loca 225 loca 224 loca 223 loca 222 loca 221 loca 220 locar12 0 loca 256 loca 255 loca 254 loca 253 loca 252 loca 251 loca 250 0 loca 246 loca 245 loca 244 loca 243 loca 242 loca 241 loca 240 locar13 0 loca 276 loca 275 loca 274 loca 273 loca 272 loca 271 loca 270 0 loca 266 loca 265 loca 264 loca 263 loca 262 loca 261 loca 260 locar14 0 loca 296 loca 295 loca 294 loca 293 loca 292 loca 291 loca 290 0 loca 286 loca 285 loca 284 loca 283 loca 282 loca 281 loca 280 locar15 0 loca 316 loca 315 loca 314 loca 313 loca 312 loca 311 loca 310 0 loca 306 loca 305 loca 304 loca 303 loca 302 loca 301 loca 300
data sheet MT90868 41 zarlink semiconductor inc.
MT90868 data sheet 42 zarlink semiconductor inc. name description locay6 - locay0 (see note 1) local output channel advancement bits 6 - 0: the binary value of these seven bits defines the local output channel advancement of the local data outputs. the output channel advancement can be selected from ch0 to ch127 before the local frame boundary. the local output channel advancement value is only valid when the locaen bit is high in the control register. note 1: y denotes a lsto stream number from 32 to 63. table 10 - local output channel advancement registers (locar15 to locar31) read/write address: 0032 h - 00041 h reset value: 0000 h 1514131211109876543210 locar16 0 loca 336 loca 335 loca 334 loca 333 loca 332 loca 331 loca 330 0 loca 326 loca 325 loca 324 loca 323 loca 322 loca 321 loca 320 locar17 0 loca 356 loca 355 loca 354 loca 353 loca 352 loca 351 loca 350 0 loca 346 loca 345 loca 344 loca 343 loca 342 loca 341 loca 340 locar18 0 loca 376 loca 375 loca 374 loca 373 loca 372 loca 371 loca 370 0 loca 366 loca 365 loca 364 loca 363 loca 362 loca 361 loca 360 locar19 0 loca 396 loca 395 loca 394 loca 393 loca 392 loca 391 loca 390 0 loca 386 loca 385 loca 384 loca 383 loca 382 loca 381 loca 380 locar20 0 loca 416 loca 415 loca 414 loca 413 loca 412 loca 411 loca 410 0 loca 406 loca 405 loca 404 loca 403 loca 402 loca 401 loca 400 locar21 0 loca 436 loca 435 loca 434 loca 433 loca 432 loca 431 loca 430 0 loca 426 loca 425 loca 424 loca 423 loca 422 loca 421 loca 420 locar22 0 loca 456 loca 455 loca 454 loca 453 loca 452 loca 451 loca 450 0 loca 446 loca 445 loca 444 loca 443 loca 442 loca 441 loca 440 locar23 0 loca 476 loca 475 loca 474 loca 473 loca 472 loca 471 loca 470 0 loca 466 loca 465 loca 464 loca 463 loca 462 loca 461 loca 460 locar24 0 loca 496 loca 495 loca 494 loca 493 loca 492 loca 491 loca 490 0 loca 486 loca 485 loca 484 loca 483 loca 482 loca 481 loca 480 locar25 0 loca 516 loca 515 loca 514 loca 513 loca 512 loca 511 loca 510 0 loca 506 loca 505 loca 504 loca 503 loca 502 loca 501 loca 500 locar26 0 loca 536 loca 535 loca 534 loca 533 loca 532 loca 531 loca 530 0 loca 526 loca 525 loca 524 loca 523 loca 522 loca 521 loca 520 locar27 0 loca 556 loca 555 loca 554 loca 553 loca 552 loca 551 loca 550 0 loca 546 loca 545 loca 544 loca 543 loca 542 loca 541 loca 540 locar28 0 loca 576 loca 575 loca 574 loca 573 loca 572 loca 571 loca 570 0 loca 566 loca 565 loca 564 loca 563 loca 562 loca 561 loca 560 locar29 0 loca 596 loca 595 loca 594 loca 593 loca 592 loca 591 loca 590 0 loca 586 loca 585 loca 584 loca 583 loca 582 loca 581 loca 580 locar30 0 loca 616 loca 615 loca 614 loca 613 loca 612 loca 611 loca 610 0 loca 606 loca 605 loca 604 loca 603 loca 602 loca 601 loca 600 locar31 0 loca 636 loca 635 loca 634 loca 633 loca 632 loca 631 loca 630 0 loca 626 loca 625 loca 624 loca 623 loca 622 loca 621 loca 620
data sheet MT90868 43 zarlink semiconductor inc. name description lidn4 - lidn0 (see note 1) local input bit delay bits 4 - 0: the binary value of these five bits defines the local input bit delay of the lsti inputs. the local input bit delay can be selected from 0 to 7 3/4 c8o clock periods. see table 13 for details note 1: n denotes a lsti stream number from 0 to 47. table 11 - local input bit delay registers (lidr0 to lidr15) read/write address: 0042 h - 00051 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lidr0 0 lid 24 lid 23 lid 22 lid 21 lid 20 lid 14 lid 13 lid1 2 lid 11 lid 10 lid 04 lid 03 lid 02 lid 01 lid 00 lidr1 0 lid 54 lid 53 lid 52 lid 51 lid 50 lid 44 lid 43 lid4 2 lid 41 lid 40 lid 34 lid 33 lid 32 lid 31 lid 30 lidr2 0 lid 84 lid 83 lid 82 lid 81 lid 80 lid 74 lid 73 lid7 2 lid 71 lid 70 lid 64 lid 63 lid 62 lid 61 lid 60 lidr3 0 lid 114 lid 113 lid 112 lid 111 lid 110 lid 104 lid 103 lid1 02 lid 101 lid 100 lid 94 lid 93 lid 92 lid 91 lid 90 lidr4 0 lid 144 lid 143 lid 142 lid 141 lid 140 lid 134 lid 133 lid1 32 lid 131 lid 130 lid 124 lid 123 lid 122 lid 121 lid 120 lidr5 0 lid 174 lid 173 lid 172 lid 171 lid 170 lid 164 lid 163 lid1 62 lid 161 lid 160 lid 154 lid 153 lid 152 lid 151 lid 150 lidr6 0 lid 204 lid 203 lid 202 lid 201 lid 200 lid 194 lid 193 lid1 92 lid 191 lid 190 lid 184 lid 183 lid 182 lid 181 lid 180 lidr7 0 lid 234 lid 233 lid 232 lid 231 lid 230 lid 224 lid 223 lid2 22 lid 221 lid 220 lid 214 lid 213 lid 212 lid 211 lid 210 lidr8 0 lid 264 lid 263 lid 262 lid 261 lid 260 lid 254 lid 253 lid2 52 lid 251 lid 250 lid 244 lid 243 lid 242 lid 241 lid 240 lidr9 0 lid 294 lid 293 lid 292 lid 291 lid 290 lid 284 lid 283 lid2 82 lid 281 lid 280 lid 274 lid 273 lid 272 lid 271 lid 270 lidr10 0 lid 324 lid 323 lid 322 lid 321 lid 320 lid 314 lid 313 lid3 12 lid 311 lid 310 lid 304 lid 303 lid 302 lid 301 lid 300 lidr11 0 lid 354 lid 353 lid 352 lid 351 lid 350 lid 344 lid 343 lid3 42 lid 341 lid 340 lid 334 lid 333 lid 332 lid 331 lid 330 lidr12 0 lid 384 lid 383 lid 382 lid 381 lid 380 lid 374 lid 373 lid3 72 lid 371 lid 370 lid 364 lid 363 lid 362 lid 361 lid 360 lidr13 0 lid 414 lid 413 lid 412 lid 411 lid 410 lid 404 lid 403 lid4 02 lid 401 lid 400 lid 394 lid 393 lid 392 lid 391 lid 390 lidr14 0 lid 444 lid 443 lid 442 lid 441 lid 440 lid 434 lid 433 lid4 32 lid 431 lid 430 lid 424 lid 423 lid 422 lid 421 lid 420 lidr15 0 lid 474 lid 473 lid 472 lid 471 lid 470 lid 464 lid 463 lid4 62 lid 461 lid 460 lid 454 lid 453 lid 452 lid 451 lid 450
MT90868 data sheet 44 zarlink semiconductor inc. name description lidn4 - lidn0 (see note 1) local input bit delay bits 4 - 0: the binary value of these five bits defines the local input bit delay of the lsti inputs. the local input bit delay can be selected from 0 to 7 3/4 c8o clock periods. see table 13 for details. note 1: n denotes a lsti stream number from 48 to 63. table 12 - local input bit delay registers (lidr16 to lidr21) local input delay corresponding delay bits c8o (period) 8.192mb/s (bit) lidn4 lidn3 lidn2 lidn1 lidn0 0 (default) 0 00000 1/4 1/4 00001 1/2 1/2 0 0 0 1 0 3/4 3/4 0 0 0 1 1 1 1 00100 1 1/4 1 1/4 00101 1 1/2 1 1/2 0 0 1 1 0 1 3/4 1 3/4 0 0 1 1 1 2 2 01000 2 1/4 2 1/4 01001 2 1/2 2 1/2 0 1 0 1 0 2 3/4 2 3/4 0 1 0 1 1 3 3 01100 3 1/4 3 1/4 01101 table 13 - local input bit delay programming table read/write address: 0052 h - 00057 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lidr16 0 lid 504 lid 503 lid 502 lid 501 lid 500 lid 494 lid 493 lid4 92 lid 491 lid 490 lid 484 lid 483 lid 482 lid 481 lid 480 lidr17 0 lid 534 lid 533 lid 532 lid 531 lid 530 lid 524 lid 523 lid5 22 lid 521 lid 520 lid 514 lid 513 lid 512 lid 511 lid 510 lidr18 0 lid 564 lid 563 lid 562 lid 561 lid 560 lid 554 lid 553 lid5 52 lid 551 lid 550 lid 544 lid 543 lid 542 lid 541 lid 540 lidr19 0 lid 594 lid 593 lid 592 lid 591 lid 590 lid 584 lid 583 lid5 82 lid 581 lid 580 lid 574 lid 573 lid 572 lid 571 lid 570 lidr20 0 lid 624 lid 623 lid 622 lid 621 lid 620 lid 614 lid 613 lid6 12 lid 611 lid 610 lid 604 lid 603 lid 602 lid 601 lid 600 lidr2100000000000lid 634 lid 633 lid 632 lid 631 lid 630
data sheet MT90868 45 zarlink semiconductor inc. 3 1/2 3 1/2 0 1 1 1 0 3 3/4 3 3/4 0 1 1 1 1 4 4 10000 4 1/4 4 1/4 10001 4 1/2 4 1/2 1 0 0 1 0 4 3/4 4 3/4 1 0 0 1 1 5 5 10100 5 1/4 5 1/4 10101 5 1/2 5 1/2 1 0 1 1 0 5 3/4 5 3/4 1 0 1 1 1 6 6 11000 6 1/4 6 1/4 11001 6 1/2 6 1/2 1 1 0 1 0 6 3/4 6 3/4 1 1 0 1 1 7 7 11100 7 1/4 7 1/4 11101 7 1/2 7 1/2 1 1 1 1 0 7 3/4 7 3/4 1 1 1 1 1 local input delay corresponding delay bits c8o (period) 8.192mb/s (bit) lidn4 lidn3 lidn2 lidn1 lidn0 table 13 - local input bit delay programming table (continued)
MT90868 data sheet 46 zarlink semiconductor inc. name description bidn4 - bidn0 (see note 1) backplane input bit delay bits 4 - 0: the binary value of these five bits defines the backplane input bit delay of the bsti inputs. the backplane input bit delay can be selected from 0 to 3 7/8 c8i clock periods. see table 16 for details. note 1: n denotes a bsti stream number from 0 to 17. table 14 - backplane input bit delay registers (bidr0 to bidr5) read/write address: 0058 h - 0005d h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bidr0 0 bid 24 bid 23 bid 22 bid 21 bid 20 bid 14 bid 13 bid 12 bid 11 bid 10 bid 04 bid 03 bid 02 bid 01 bid 00 bidr1 0 bid 54 bid 53 bid 52 bid 51 bid 50 bid 44 bid 43 bid 42 bid 41 bid 40 bid 34 bid 33 bid 32 bid 31 bid 30 bidr2 0 bid 84 bid 83 bid 82 bid 81 bid 80 bid 74 bid 73 bid 72 bid 71 bid 70 bid 64 bid 63 bid 62 bid 61 bid 60 bidr3 0 bid 114 bid 113 bid 112 bid 111 bid 110 bid 104 bid 103 bid 102 bid 101 bid 100 bid 94 bid 93 bid 92 bid 91 bid 90 bidr4 0 bid 144 bid 143 bid 142 bid 141 bid 140 bid 134 bid 133 bid 132 bid 131 bid 130 bid 124 bid 123 bid 122 bid 121 bid 120 bidr5 0 bid 174 bid 173 bid 172 bid 171 bid 170 bid 164 bid 163 bid 162 bid 161 bid 160 bid 154 bid 153 bid 152 bid 151 bid 150
data sheet MT90868 47 zarlink semiconductor inc. name description bidn4 - bidn0 (see note 1) backplane input bit delay bits 4 - 0: the binary value of these five bits defines the backplane input bit delay of the bsti inputs. the backplane input bit delay can be selected from 0 to 3 7/8 c8i clock periods. see table 16 for details. note 1: n denotes a bsti stream number from 18 to 63. table 15 - backplane input bit delay registers (bidr0 to bidr5) read/write address: 005e h - 0006d h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bidr6 0 bid 204 bid 203 bid 202 bid 201 bid 200 bid 194 bid 193 bid 192 bid 191 bid 190 bid 184 bid 183 bid 182 bid 181 bid 180 bidr7 0 bid 234 bid 233 bid 232 bid 231 bid 230 bid 224 bid 223 bid 222 bid 221 bid 220 bid 214 bid 213 bid 212 bid 211 bid 210 bidr8 0 bid 264 bid 263 bid 262 bid 261 bid 260 bid 254 bid 253 bid 252 bid 251 bid 250 bid 244 bid 243 bid 242 bid 241 bid 240 bidr9 0 bid 294 bid 293 bid 292 bid 291 bid 290 bid 284 bid 283 bid 282 bid 281 bid 280 bid 274 bid 273 bid 272 bid 271 bid 270 bidr10 0 bid 324 bid 323 bid 322 bid 321 bid 320 bid 314 bid 313 bid 312 bid 311 bid 310 bid 304 bid 303 bid 302 bid 301 bid 300 bidr11 0 bid 354 bid 353 bid 352 bid 351 bid 350 bid 344 bid 343 bid 342 bid 341 bid 340 bid 334 bid 333 bid 332 bid 331 bid 330 bidr12 0 bid 384 bid 383 bid 382 bid 381 bid 380 bid 374 bid 373 bid 372 bid 371 bid 370 bid 364 bid 363 bid 362 bid 361 bid 360 bidr13 0 bid 414 bid 413 bid 412 bid 411 bid 410 bid 404 bid 403 bid 402 bid 401 bid 400 bid 394 bid 393 bid 392 bid 391 bid 390 bidr14 0 bid 444 bid 443 bid 442 bid 441 bid 140 bid 434 bid 433 bid 432 bid 431 bid 430 bid 424 bid 423 bid 422 bid 421 bid 420 bidr15 0 bid 474 bid 473 bid 472 bid 471 bid 470 bid 464 bid 463 bid 462 bid 461 bid 460 bid 454 bid 453 bid 452 bid 451 bid 450 bidr16 0 bid 504 bid 503 bid 502 bid 501 bid 500 bid 494 bid 493 bid 492 bid 491 bid 490 bid 484 bid 483 bid 482 bid 481 bid 480 bidr17 0 bid 534 bid 533 bid 532 bid 531 bid 530 bid 524 bid 523 bid 522 bid 521 bid 520 bid 514 bid 513 bid 512 bid 511 bid 510 bidr18 0 bid 564 bid 563 bid 562 bid 561 bid 560 bid 554 bid 553 bid 552 bid 551 bid 550 bid 544 bid 543 bid 542 bid 541 bid 540 bidr19 0 bid 594 bid 593 bid 592 bid 591 bid 590 bid 584 bid 583 bid 582 bid 581 bid 580 bid 574 bid 573 bid 572 bid 571 bid 570 bidr20 0 bid 624 bid 623 bid 622 bid 621 bid 620 bid 614 bid 613 bid 612 bid 611 bid 610 bid 604 bid 603 bid 602 bid 601 bid 600 bidr2100000000000bid 634 bid 633 bid 632 bid 631 bid 630
MT90868 data sheet 48 zarlink semiconductor inc. backplane input delay corresponding delay bits c8i (period) 16.384mb/s (bit) 32.768mb/s (bit) bidn4 bidn3 bidn 2 bidn1 bidn0 0 (default) 0 0 0 0 0 0 0 1/8 1/4 1/2 00001 1/4 1/2 1 0 0 0 1 0 3/8 3/4 1 1/2 0 0 0 1 1 1/2 1 2 00100 5/8 1 1/4 2 1/2 00101 3/4 1 1/2 3 0 0 1 1 0 7/8 1 3/4 3 1/2 0 0 1 1 1 1 2 4 01000 1 1/8 2 1/4 4 1/2 01001 1 1/4 2 1/2 5 0 1 0 1 0 1 3/8 2 3/4 5 1/2 0 1 0 1 1 1 1/2 3 6 01100 1 5/8 3 1/4 6 1/2 01101 1 3/4 3 1/2 7 0 1 1 1 0 1 7/8 3 3/4 7 1/2 0 1 1 1 1 24 n/a 10000 2 1/8 4 1/4 10001 2 1/4 4 1/2 1 0 0 1 0 2 3/8 4 3/4 1 0 0 1 1 2 1/2 5 10100 2 5/8 5 1/4 10101 2 3/4 5 1/2 1 0 1 1 0 2 7/8 5 3/4 1 0 1 1 1 3 6 11000 3 1/8 6 1/4 11001 3 1/4 6 1/2 1 1 0 1 0 3 3/8 6 3/4 1 1 0 1 1 3 1/2 7 11100 3 5/8 7 1/4 11101 3 3/4 7 1/2 1 1 1 1 3 7/8 7 3/4 1 1 1 1 table 16 - backplane input bit delay programming table
data sheet MT90868 49 zarlink semiconductor inc. name description loan1 - loan0 (see note 1) local output advancement bits 1 - 0: the binary value of these two bits defines the local output advancement of the lsto outputs. th e local output advancement can be selected from 0 to - 3/8 c8o clock periods. see table 18 for details. note 1: n denotes a lsto stream number from 0 to 63. table 17 - local output advancement registers (loar0 to loar7) local output advancement corresponding advancement bits c8o (period) 8.192mb/s (bit) loan1 loan0 0 (default) 0 0 0 - 1/8 - 1/8 0 1 - 1/4 - 1/4 1 0 - 3/8 - 3/8 1 1 table 18 - local output advancement programming table read/write address: 006e h - 00075 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 loar0 loa 71 loa 70 loa 61 loa 60 loa 51 loa 50 loa 41 loa 40 loa 31 loa 30 loa 21 loa 20 loa 11 loa 10 loa 01 loa 00 loar1 loa 151 loa 150 loa 141 loa 140 loa 131 loa 130 loa 121 loa 120 loa 111 loa 110 loa 101 loa 100 loa 91 loa 90 loa 81 loa 80 loar2 loa 231 loa 230 loa 221 loa 220 loa 211 loa 210 loa 201 loa 200 loa 191 loa 190 loa 181 loa 180 loa 171 loa 170 loa 161 loa 160 loar3 loa 311 loa 310 loa 301 loa 300 loa 291 loa 290 loa 281 loa 280 loa 271 loa 270 loa 271 loa 260 loa 251 loa 250 loa 241 loa 240 loar4 loa 391 loa 390 loa 381 loa 380 loa 371 loa 370 loa 361 loa 360 loa 351 loa 350 loa 341 loa 340 loa 331 loa 330 loa 321 loa 320 loar5 loa 471 loa 470 loa 461 loa 460 loa 451 loa 450 loa 441 loa 440 loa 431 loa 430 loa 421 loa 420 loa 411 loa 410 loa 401 loa 400 loar6 loa 551 loa 550 loa 541 loa 540 loa 531 loa 530 loa 521 loa 520 loa 511 loa 510 loa 501 loa 500 loa 491 loa 490 loa 481 loa 480 loar7 loa 631 loa 630 loa 621 loa 620 loa 611 loa 610 loa 601 loa 600 loa 591 loa 590 loa 581 loa 580 loa 571 loa 570 loa 561 loa 560
MT90868 data sheet 50 zarlink semiconductor inc. name description boan1 - boan0 (see note 1) backplane output advancement bits 1 - 0: the binary value of these two bits defines the backplane output advancement of the bsto outputs. the backplane output advancement can be selected from 0 to - 3/8 c8i clock periods. see table 20 for details. note 1: n denotes a bsto stream number from 0 to 63. table 19 - backplane output advancement registers (boar0 to boar7) backplane output advancement corresponding advancement bits c8i (period) 16.384mb/s (bit) 32.768mb/s (bit) boan1 boan0 0 (default) 0 0 0 0 - 1/8 - 1/4 - 1/2 0 1 - 1/4 - 1/2 - 1 1 0 - 3/8 - 3/4 - 1 1/2 11 table 20 - backplane output advancement programming table read/write address: 0076 h - 0007d h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 boar0 boa 71 boa 70 boa 61 boa 60 boa 51 boa 50 boa 41 boa 40 boa 31 boa 30 boa 21 boa 20 boa 11 boa 10 boa 01 boa 00 boar1 boa 151 boa 150 boa 141 boa 140 boa 131 boa 130 boa 121 boa 120 boa 111 boa 110 boa 101 boa 100 boa 91 boa 90 boa 81 boa 80 boar2 boa 231 boa 230 boa 221 boa 220 boa 211 boa 210 boa 201 boa 200 boa 191 boa 190 boa 181 boa 180 boa 171 boa 170 boa 161 boa 160 boar3 boa 311 boa 310 boa 301 boa 300 boa 291 boa 290 boa 281 boa 280 boa 271 boa 270 boa 271 boa 260 boa 251 boa 250 boa 241 boa 240 boar4 boa 391 boa 390 boa 381 boa 380 boa 371 boa 370 boa 361 boa 360 boa 351 boa 350 boa 341 boa 340 boa 331 boa 330 boa 321 boa 320 boar5 boa 471 boa 470 boa 461 boa 460 boa 451 boa 450 boa 441 boa 440 boa 431 boa 430 boa 421 boa 420 boa 411 boa 410 boa 401 boa 400 boar6 boa 551 boa 550 boa 541 boa 540 boa 531 boa 530 boa 521 boa 520 boa 511 boa 510 boa 501 boa 500 boa 491 boa 490 boa 481 boa 480 boar7 boa 631 boa 630 boa 621 boa 620 boa 611 boa 610 boa 601 boa 600 boa 591 boa 590 boa 581 boa 580 boa 571 boa 570 boa 561 boa 560
data sheet MT90868 51 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 - 6 bdsb5 - 0 backplane data stream address bits for stream b: the binary value of these bits refers to the backplane input data stream. 5 - 0 bdsa5 - 0 backplane data stream address bits for stream a: the binary value of these bits refers to the backplane input data stream. table 21 - backplane data input selection register (bdisr) bits bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 - 6 bdsd5 - 0 backplane data stream address bits for stream d: the binary value of these bits refers to the backplane input data stream. 5 - 0 bdsc5 - 0 backplane data stream address bits for stream c: the binary value of these bits refers to the backplane input data stream. table 22 - backplane data memory read selection regist er (bdmrsr) bits bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 - 6 ldsf5 - 0 local data stream address bits for stream f: the binary value of these bits refers to the local input data stream. 5 - 0 ldse5 - 0 local data stream address bits for stream e: the binary value of these bits refers to the local input data stream. table 23 - local data memory read selection register (ldmrsr) bits read/write address: 007e h reset value: 0000 h 1514131211109876543210 0000bds b5 bds b4 bds b3 bds b2 bds b1 bds b0 bds a5 bds a4 bds a3 bds a2 bds a1 bds a0 read/write address: 007f h reset value: 0000 h 1514131211109876543210 0000bds d5 bds d4 bds d3 bds d2 bds d1 bds d0 bds c5 bds c4 bds c3 bds c2 bds c1 bds c0 read/write address: 0080 h reset value: 0000 h 1514131211109876543210 0000lds f5 lds f4 lds f3 lds f2 lds f1 lds f0 lds e5 lds e4 lds e3 lds e2 lds e1 lds e0
MT90868 data sheet 52 zarlink semiconductor inc. bit name description 15 - 13 unused reserved. in normal functional mode, these bits must be set to zero. 12 - 7 lbrsa5 - 0 local ber receive stream address bits: the binary value of these bits refers to the local input stream which receives the ber data. 6 - 0 lbrca6 - 0 local ber receive channel address bits: the binary value of these bits refers to the local input channel in which the ber data starts to be compared. table 24 - local ber start receiving register (lbsrr) bits bit name description 15 - 7 unused reserved. in normal functional mode, these bits must be set to zero. 6 - 0 lbl6 - 0 local ber length bits: the binary value of these bits refers to the number of chan- nels, the ber data will last. the maximum number of local ber channels is 127. table 25 - local ber length register (lblr) bits bit name description 15 - 0 lbc15 - 0 local bit error rate count: the binary value of these bits refers to the local bit error count. table 26 - local ber count register (lbcr) bits read/write address: 0081 h reset value: 0000 h 1514131211109876543210 000lbr sa5 lbr sa4 lbr sa3 lbr sa2 lbr sa1 lbr sa0 lbr ca6 lbr ca5 lbr ca4 lbr ca3 lbr ca2 lbr ca1 lbr ca0 read/write address: 0082 h reset value: 0000 h 1514131211109876543210 000000000lbl6lbl5lbl4lbl3lbl2lbl1lbl0 read/write address: 0083 h reset value: 0000 h 1514131211109876543210 lbc 15 lbc 14 lbc 13 lbc 12 lbc 11 lbc 10 lbc 9 lbc 8 lbc 7 lbc 6 lbc 5 lbc 4 lbc 3 lbc 2 lbc 1 lbc 0
data sheet MT90868 53 zarlink semiconductor inc. bit name description 15 unused reserved. in normal functional mode, th is bit must be set to zero. 14 - 9 bbrsa5 - 0 backplane ber receive stream address bits: the binary value of these bits refers to the backplane input stream which receives the ber data. 8 - 0 bbrca8 - 0 backplane ber receive channel address bits: the binary value of these bits refers to the backplane input channel in which the ber data starts to be compared. table 27 - backplane ber start receiving register (bbsrr) bits bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8 - 0 bbl8 - 0 backplane ber length bits: the binary value of these bits refers to the number of channels, the ber data will last. the maximum number of backplane ber channels is 511. table 28 - backplane ber length register (bblr) bits bit name description 15 - 0 bbc15 - 0 backplane bit e rror rate count: the binary value of these bits refers to the back- plane bit error count. table 29 - backplane ber count register (bbcr) bits read/write address: 0084 h reset value: 0000 h 1514131211109876543210 0 bbr sa5 bbr sa4 bbr sa3 bbr sa2 bbr sa1 bbr sa0 bbr ca8 bbr ca7 bbr ca6 bbr ca5 bbr ca4 bbr ca3 bbr ca2 bbr ca1 bbr ca0 read/write address: 0085 h reset value: 0000 h 1514131211109876543210 0 0 0 0 0 0 0 bbl8 bbl7 bbl6 bbl5 bbl4 bbl3 bbl2 bbl1 bbl0 read/write address: 0086 h reset value: 0000 h 1514131211109876543210 bbc 15 bbc 14 bbc 13 bbc 12 bbc 11 bbc 10 bbc 9 bbc 8 bbc 7 bbc 6 bbc 5 bbc 4 bbc 3 bbc 2 bbc 1 bbc 0
MT90868 data sheet 54 zarlink semiconductor inc. bit name description 15 lmsc local mode selection control: when this bit and the ltm0, ltm1 bits in the local connection memory high are low, the "backplane-to-local" switching is enabled. when this bit is high, the content of the ltm0, ltm1 bits in the local connection memory high select one of the operation modes described in the table below: . 14 - 9 lsab5 - 0 local source stream address bits: the binary value of these 6 bits represents the data stream number for the source (local or backplane) connection. 8 - 0* lcab8 - 0 local source channel address bits: the binary value of these 9 bits represents the channel number that is the source (local or backplane) connection. *note: only bit 7-0 will be used for per-channel message mode. table 30 - local connection memory low (lcml) bits bit name description 15 - 2 unused reserved. 1 - 0 ltm1 - 0 local tm bits: these two bits control the lsto output . table 31 - local connection memory high (lcmh) bits 1514131211109876543210 lmsc lsab 5 lsab 4 lsab 3 lsab 2 lsab 1 lsab 0 lcab 8 lcab 7 lcab 6 lcab 5 lcab 4 lcab 3 lcab 2 lcab 1 lcab 0 lmsc ltm1 bit in lcmh ltm0 bit in lcmh per-channel operation mode 0 0 0 'backplane-to-local' switching lmsc ltm1 bit in lcmh ltm0 bit in lcmh per-channel operation mode 1 0 0 'local-to-local switching' 1 0 1 high impedance 1 1 0 msg mode 1 1 1 ber test mode 1514131211109876543210 0 0000000000000ltm 1 ltm 0 ltm1 ltm0 lmsc bit in lcml per-channel operation mode 0 0 0 'backplane-to-local' switching 0 0 1 'local-to-local' switching 0 1 1 high impedance 1 0 1 msg mode 1 1 1 ber test mode
data sheet MT90868 55 zarlink semiconductor inc. bit name description 15 bsrc backplane source control bit: when this bit is low, the "local-to-backplane" switching is enabled and the source is from the local input port. 14 - 13 btm1 - 0 backplane tm bits: these two bits control the backplane outputs . 12 - 7* bsab5 - 0 backplane source stream address bits: the binary value of these 6 bits repre- sents the local data input stream number. 6 - 0 * bcab6 - 0 source channel address bits: the binary value of these 7 bits represents the local input channel number. *note: only bit 7-0 will be used for per-channel message mode. *note: the last channel (ch255 or ch511) of the backplane output streams bsto60 to bsto63 or bsto58 to bsto63 contains invalid output data when operated in the 16mb/s or 32mb/s mode respectively. avoid using the last channel of these streams for the "local-to-backplane" switching . table 32 - backplane connection memory (bcm) bits for "local-to-backplane" switching 1514131211109876543210 bsrc = 0 btm 1 btm 0 bsa b5 bsa b4 bsa b3 bsa b2 bsa b1 bsa b0 bca b6 bca b5 bca b4 bca b3 bca b2 bca b1 bca b0 btm1 btm0 per-channel operation mode 0 0 normal output 0 1 tristate/driven-high (see bit 15 (bhiz) in table 5) 1 0 msg mode 11 ber test mode
MT90868 data sheet 56 zarlink semiconductor inc. * exceeding these values may cause permanent damage. func tional operation under these co nditions is not implied. bit name description 15 bsrc backplane source control bit: when this bit is high, the "backplane-to backplane" switching is enabled and the source is from the backplane input port. 14 - 13 btm1 - 0 backplane tm bits: these two bits control the backplane outputs . 12-10 unused reserved. set to zero for normal operation. 9 bsab0 backplane source stream address bits: when this bit is low, the source stream (stream a) is selected. stream a is defined in the bdisr register. when this bit is high, the source stream (stream b) is selected. stream b is defined in the bdisr register. 8 - 0 * bcab8 - 0 source channel address bits: the binary value of these 9 bits represents the local input channel number. *note: only bit 7-0 will be used for per-channel message mode. table 33 - backplane connection memory (bcm) bits for "backplane-to-backplane" switching absolute maximum ratings* parameter symbo lmin maxunits 1 core supply voltage v dd_core -0.5 2.5 v 2 i/o supply voltage v dd_io -0.5 5.0 v 3 input voltage v i_3v -0.5 v dd + 0.5 v 4 input voltage (5v tolerant inputs) v i_5v -0.5 7.0 v 5 continuous current at digital outputs i o 15 ma 6 package power dissipation p d 2w 7 storage temperature t s - 55 +125 c 1514131211109876543210 bsrc = 1 btm 1 btm 0 000bsa b0 bca b8 bca b7 bca b6 bca b5 bca b4 bca b3 bca b2 bca b1 bca b0 btm1 btm0 per-channel operation mode 0 0 normal output 0 1 tristate/driven-high (see bit 15 (bhiz) in table 5) 1 0 msg mode 11 ber test mode
data sheet MT90868 57 zarlink semiconductor inc. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figure: at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production * testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). ? characteristics are over recommended operating conditions unless otherwise stated. recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym min typ ? max units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_core 1.71 1.8 1.89 v 3 positive supply v dd_io 3.0 3.3 3.6 v 4 input voltage v i 03.3v dd_io v 5 input voltage on 5v tolerant inputs v i_5v 05.05.5v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 core supply current i dd_core 600 ma output unloaded 2 io pad supply current i dd_io 380 ma output unloaded 3 input high voltage v ih 2.0 v 4 input low voltage v il 0.8 v 5 input leakage (input pins) input leakage (bi-directional pins) i il i bl 5 5 a a 0 MT90868 data sheet 58 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - backplane and local clock timing characteristic sym min typ ? max units notes 1 backplane frame pulse width t bfpw 20 122 230 ns 2 backplane frame pulse setup time before c8i clock falling edge t bfps 10 90 ns 3 backplane frame pulse hold time from c8i clock falling edge t bfph 10 90 ns 4c8i clock period t bcp 120 122 124 ns 5c8i clock pulse width high t bch 50 61 70 ns 6c8i clock pulse width low t bcl 50 61 70 ns 7c8i clock rise/fall time t rc8i , t fc8i 023 ns 8c8i cycle to cycle variation t cvc8i 026 ns 9fp4o width t fpw4 220 244 270 ns c l =30pf 10 fp4o output setup from the fp4o falling edge to the c4o falling edge t fosf4 110 122 135 ns 11 fp4o output hold from the c4o falling edge to the fp4o rising edge t fohr4 120 122 145 ns 12 c4o clock period t cp4 239 244 249 ns 13 c4o clock pulse width high t ch4 110 122 135 ns 14 c4o clock pulse width low t cl4 110 122 135 ns 15 c4o clock rise/fall time t rc4o , t fc4o 7ns 16 fp8o width t fpw8 111 122 133 ns 17 fp8o output setup from the fp8o falling edge to the c4o falling edge t fosf8 50 61 75 ns 18 fp8o output hold from the c4o falling edge to the fp8o rising edge t fohr8 60 61 80 ns 19 c8o clock period t cp8 119 122 125 ns 20 c8o clock pulse width high t ch8 55 61 67 ns 21 c8o clock pulse width low t cl8 55 61 67 ns 22 c8o clock rise/fall time t rc8o , t fc8o 7ns 23 fp16o width t fpw16 55 61 67 ns 24 fp16o output setup from the fp16o falling edge to the c4o falling edge t fosf16 20 30 45 ns 25 fp16o output hold from the c4o falling edge to the fp16o rising edge t fohr16 30 40 50 ns 26 c16o clock period t cp16 59 61 63 ns 27 c16o clock pulse width high t ch16 27 30 33 ns 28 c16o clock pulse width low t cl16 27 30 33 ns 29 c16o clock rise/fall time t rc16o , t fc16o 7ns
data sheet MT90868 59 zarlink semiconductor inc. figure 18 - backplane and local clock timing diagram t bfpw fp8i t bfph c8i t fc8i t bch t bcl t bfps t rc8i t fpw8 t fohr8 t fosf8 t fpw4 t fohr4 t fosf4 t fohr16 t fosf16 fp4o c4o fp16o c16o fp8o c8o t cl4 t ch4 t ch8 t lcl8 t cl16 t ch16 t fpw16 t lcp4 t cp8 t lcp16 t bcp t fc8o t rc8o t rc16o t fc16o t rc4o t fc4o backplane port timing local port timing
MT90868 data sheet 60 zarlink semiconductor inc. ? characteristics are over recommended ope rating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - backplane data timing for the 16mb/s mode characteristic sym min typ ? max units notes 1 input data sampling point for bit 0, bit 2, bit 4 and bit 6 t ids0 t ids2 t ids4 t ids6 106 107 108 ns 2 input data sampling point for bit 1, bit 3, bit 5 and bit 7 t ids1 t ids3 t ids5 t ids7 45 46 47 ns 3 backplane serial input set-up time t sis 3.5 ns 4 backplane serial input hold time t sih 1.5 ns 5 backplane serial output delay for bit 0, bit 2, bit 4 and bit 6 t sod0 t sod2 t sod4 t sod6 68 73.5 79 ns c l =30pf 6 backplane serial output delay for bit 1, bit 3, bit 5 and bit 7 t sod1 t sod3 t sod5 t sod7 712.518 ns see figure 19 in the next page for the 16mb/s mode backplane data timing diagram.
data sheet MT90868 61 zarlink semiconductor inc. figure 19 - backplane data timing diagram (16mb/s mode) fp8i c8i t sis t sih bit6 ch0 bit7 ch0 bit5 ch0 bit0 ch255 t sod7 bit7 ch0 bit6 ch0 bit5 ch0 bit0 ch255 bsti0 - 63 bsto0 - 63 t ids6 t ids7 16.384mb/s 16.384mb/s t ids5 t sod5 t sod6 bit4 ch0 bit4 ch0 t ids4 t sod4 bit3 ch0 bit3 ch0 bit2 ch0 t ids3 t sod3 t ids2 t sod2 bit2 ch0 bit2 ch0 bit1 ch0 bit2 ch0 bit1 ch0 t ids1 t sod1 bit0 ch0 bit0 ch0 t ids0 t sod0 v tt v tt c8i bsto0 - 63 16.384mb/s
MT90868 data sheet 62 zarlink semiconductor inc. ? characteristics are over recommended ope rating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. figure 20 - backplane data timing diagram (32mb/s mode) ac electrical characteristics ? - backplane data timing for the 32mb/s mode characteristic sym min typ ? max units notes 1 input data sampling point for bit 0 and bit 4 t ids0 t ids4 113.5 114.5 115.5 ns 2 input data sampling point for bit 1 and bit 5 t ids1 t ids5 82.6 83.6 84.6 ns 3 input data sampling point for bit 2 and bit 6 t ids2 t ids6 52.3 53.3 54.3 ns 4 input data sampling point for bit 3 and bit 7 t ids3 t ids7 21.8 22.8 23.8 ns 5 backplane serial input set-up time t sis 3.5 ns 6 backplane serial input hold time t sih 1.5 ns 7 backplane serial output delay for bit 0 and bit 4 t sod0 t sod4 99 103.5 108 ns c l =30pf 8 backplane serial output delay for bit 1 and bit 5 t sod1 t sod5 69 73.5 78 ns 9 backplane serial output delay for bit 2 and bit 6 t sod2 t sod6 38 42.5 47 ns 10 backplane serial output delay for bit 3 and bit 7 t sod3 t sod7 8 12.5 17 ns v tt fp8i v tt c8i t sis t sod7 bit7 ch0 v tt bsti0 - 63 bsto0 - 63 t ids4 t ids7 32.768mb/s 32.768mb/s bit7 ch0 bit6 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit1 ch511 bit2 ch511 t ids5 t ids6 t sih bit6 ch0 bit5 ch0 bit7 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch511 bit1 ch511 bit2 ch511 t ids3 t ids1 t ids2 t sod5 t sod4 t sod6 t sod3 t sod2 t sod1 bit0 ch0 t ids0 bit1 ch0 bit0 ch0 t sod0 v tt t ids2 bit5 ch0 bit0 ch511
data sheet MT90868 63 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. figure 21 - local data timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. note 1: high impedance is measured by pulling to the appropriate rail with rl, with timing corrected to cancel time taken to discharge c l . figure 22 - per-channel and ode tristate control timing diagrams ac electrical characteristics ? - local data timing characteristic sym min typ ? max units notes 1 input data sampling point t ids 90 91.6 94 ns 2 local serial input set-up time t sis 3.5 ns 3 local serial input hold time t sih 1.5 ns 4 local serial output delay t sod 712.518 nsc l =30pf ac electrical characteristics ? - backplane and local output hiz timing characteristic sym min typ ? max units test conditions 1 bsto/lsto delay - active to high-z - high-z to active t dz, t zd 30 ns r l =1k, c l =30pf, see note 1 2 output driver enable (ode) delay t ode 13 25 ns r l =1k, c l =30pf, see note 1 v tt v tt fp8o c8o t sis t sih bit7 ch0 bit0 ch127 t sod bit7 ch0 lsti0 - 63 lsto0 - 63 t ids 8.192mb/s 8.192mb/s bit7 ch127 bit6 ch0 t dz bsto/lsto t zd bsto/lsto c8i /c8o v tt hiz valid data v tt hiz valid data v tt v tt hiz hiz sto ode t ode t ode valid data v tt per-channel tristate timing ode pin tristate timing
MT90868 data sheet 64 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1.8v and v dd_io at 3.3v and are for design aid only: not guaranteed and not subject to production testing. note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 23 - motorola non-multiplexed bus timing ac electrical characteristics ? - non-multiplexed microprocessor port timing characteristics sym min typ ? max units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 15 ns 3 address setup from ds falling t ads 5ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 5ns 6 address hold after ds rising t adh 510 ns 7 data setup from dta low on read t ddr 4nsc l =30pf 8 data hold on read t dhr 10 ns c l =30pf, r l =1k note 1 9 valid write data setup t wds 25 ns 10 data hold on write t dhw 8ns 11 acknowledgment delay t akd 65 70 ns c l =30pf 12 acknowledgment hold time t akh 14 20 ns c l =30pf, r l =1k, note 1 ds a0-a15 cs d0-d15 d0-d15 read write t css t csh t adh t dhr r/w t ads t rwh t akd t wds t akh dta v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data t rws t dhw t ddr
data sheet MT90868 65 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 24 - jtag test port timing diagram figure 25 - reset pin timing diagram ac electrical characteristics ? - jtag test port and reset pin timing characteristic sym min typ max units notes 1 tck clock period t tckp 200 ns 2 tck clock pulse width high t tckh 80 ns 3 tck clock pulse width low t tckl 80 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 90 ns 8 tdo output delay t tdod 30 ns c l =30pf 9trst pulse width t trstw 200 ns c l =30pf 10 reset pulse width t rstw 500 ns c l =30pf t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst t rstw reset
MT90868 data sheet 66 zarlink semiconductor inc. figure 26 - bit interleaving mode timing diagram for backplane input and output streams fp8i (8.192mhz) c8i 72 3 4 5 610 bsti0-63/sto0-63 (32mb/s) channel 0 72 3 4 5 610 channel 1 2 310 (8khz) 72 3 4 5 610 channel 2 72 3 4 5 610 channel 3 72 3 4 5 610 channel 4 72 3 4 5 610 channel 5 no bit interleaving bsti0-63 (32mb/s) ch0 bit7 ch1 bit7 ch2 bit7 ch3 bit7 ch0 bit6 ch1 bit6 ch2 bit6 ch3 bit6 ch0 bit5 ch1 bit5 ch2 bit5 ch3 bit5 ch0 bit4 ch1 bit4 ch2 bit4 ch3 bit4 ch0 bit3 ch1 bit3 ch2 bit3 ch3 bit3 ch0 bit2 ch1 bit2 ch2 bit2 ch3 bit2 ch0 bit1 ch1 bit1 ch2 bit1 ch3 bit1 ch0 bit0 ch1 bit0 ch2 bit0 ch3 bit0 ch4 bit7 ch5 bit7 ch6 bit7 ch7 bit7 ch4 bit6 ch5 bit6 ch6 bit6 ch7 bit6 ch4 bit5 ch5 bit5 ch6 bit5 ch7 bit5 ch4 bit4 ch5 bit4 ch6 bit4 ch508 bit0 ch509 bit0 ch510 bit0 ch511 bit0 channel 511 bsto0-63 (32mb/s) bit interleaving ch510 bit0 ch511 bit0 ch7 bit4 output stream advanced by -1/4 c8i by programming the boar registers bit interleaving timeslot 0 timeslot 1 ts 127 timeslot 1 timeslot 0 ch511 bit1 input stream delayed by 1/4 c8i ch509 bit0 by programming the bidr registers ch0 bit7 ch1 bit7 ch2 bit7 ch3 bit7 ch0 bit6 ch1 bit6 ch2 bit6 ch3 bit6 ch0 bit5 ch1 bit5 ch2 bit5 ch3 bit5 ch0 bit4 ch1 bit4 ch2 bit4 ch3 bit4 ch0 bit3 ch1 bit3 ch2 bit3 ch3 bit3 ch0 bit2 ch1 bit2 ch2 bit2 ch3 bit2 ch0 bit1 ch1 bit1 ch2 bit1 ch3 bit1 ch0 bit0 ch1 bit0 ch2 bit0 ch3 bit0 ch4 bit7 ch5 bit7 ch6 bit7 ch7 bit7 ch4 bit6 ch5 bit6 ch6 bit6 ch7 bit6 ch4 bit5 ch5 bit5 ch6 bit5 ch7 bit5 ch4 bit4 ch5 bit4 ch6 bit4 appendix - bit interleaving mode the bit interleaving mode performs the bit grooming function for the backplane input and output streams which have data rate of 32mb/s. this mode is enabled by setting the bit interleaving mode enable (bime) pin to one. the bit shuffling is performed for every four-channel as indicated in figure 26. the input delay and the output advancement show n in figure 26 are realized by programming the backplane input delay registers (lidr0 to lidr21) and the backplane output advancement registers (boar0 to boar7) as described in table 11 & 12 and table 20 respectively. when the bit interleaving mode is selected for the backplane port, the delay between the frame pulse signals is six 32mb/s channels plus 10 cycles of c8i. see figure 27 for the frame pulse offset timing in the bit interleaving mode. when the device is in the bit interleaving mode, the bit error rate test feature is not available fo r the backplane port bsti0 - 63 and bsto0 - 63.
data sheet MT90868 67 zarlink semiconductor inc. figure 27 - backplane and local frame pulse alignment diagram for the bit interleaving mode bsti/bsto0-63 time slot 0 fp8i c8i fp8o c8o 3 1 2 0 channel 126 5 6 74 lsti/lsto0-63 (8mb/s) 3 1 2 0 channel 127 5 6 74 channel 0 4 ts127 5 6 time slot 1 time slot 2 5 6 74 3 1 2 0 7 channel 125 11 (32mb/s) channels (32mb/s)
package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of MT90868

	To Download MT90868 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .